Bio Nguyen

Luu Nguyen (AM ’92, M ’96, SM ’99, F ’01) is the Director of Quality and Reliability at PsiQuantum since 2019, a start-up based in Palo Alto, CA, that aims at building the first large-scale, error-corrected, general-purpose silicon photonics-based quantum computer.  I drive the quality and reliability efforts around integrating a complex quantum optical system-on-a-chip, based on scalable foundry manufacturing processes.  As an integrated system, the technical challenges span control systems, cryogenics, optical design, non-linear quantum optics, optoelectronic packaging, process development, software, test and measurement, and supply chain and logistics.  I co-lead IEEE Quantum, an IEEE Future Directions initiative launched to serve as IEEE’s leading community for all projects and activities on quantum technologies.  A project plan was developed 

to address the current landscape of quantum technologies, identify challenges and opportunities, leverage and collaborate with existing initiatives, and engage the quantum community at large.  I serve on the Steering Committee for IEEE Quantum Week, the flagship conference on all quantum computing and engineering topics, and participate in many technical committees (ECTC Packaging Technologies, TC on Reliability, TC on Emerging Technologies, Rel. for Electronics & Photonics Packaging Symposium), award committees (CPMT Field Award, SMTA Society Awards, and ASME Allan Kraus Thermal Management Award, EPPD Awards), and EPS Fellows Nomination committee.  I am currently an Associate Editor for T-CPMT, and have been a Guest Editor for three past issues (Drop Testing (2007), Wafer Level Packaging (2008, 2009).)

I retired as a Fellow at Texas Instruments in 2019, where I worked on various strategic initiatives that included sensors, printed electronics, high voltage packaging, wafer-level packaging, thermal management, design-for-manufacturability, and design-for-reliability.  I graduated with a Ph.D. in Mechanical Engineering from MIT and worked at IBM Research, Philips Research, and National Semiconductor.  I have co-edited two books on packaging technologies.  I have written several book chapters, have over 70 patents and invention disclosures, and over 200 publications.  I am a Fellow of IEEE and ASME, a Fulbright Scholar (Finland 2002), a Fannie and John Hertz Fellow, and an AAAS Mass Media Science and Engineering Fellow.  I received two Best Paper of Conference Awards, one Best Poster of Conference Award, and eight IMAPS and IEMT Best Session of Conference Awards.  I have received the 2004 IEEE CPMT Outstanding Sustained Technical Contributions Award, the 2015 IEEE Outstanding Engineering Manager Award for the IEEE Region 6, and the 2018 Surface Mount Technology Association Member of Technical Distinction.  Other awards also include the 2003, 2014, 2015, and 2016 Mahboob Khan Outstanding Mentor Award from the Semiconductor Research Corporation to recognize contributions to student mentoring, research collaboration, and technology transfer.  I co-led the efforts at National Semiconductor to garner the Electronic Product Design (UK) e-Legacy “Investment in Training Award” (2007), the “Investment in Education Award” (2007), and the European Electronics Industry “Investing in People” Elektra Award (2006) for the most innovative company training scheme to foster professional development, practical training, best practices sharing, mentoring, cross-training, and e-learning among more than 2,500 engineers worldwide.