Bio Iyer

SUBRAMANIAN (SUBU) S. IYER (S’76-M’81-SM’88-F’95) is Distinguished Chancellor’s Professor and holds the Charles Reames Endowed Chair in the Electrical Engineering Department at the University of California at Los Angeles and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). He obtained his B.Tech. from IIT-Bombay, and Ph.D. from UCLA and joined the IBM T.J. Watson Research Center at Yorktown heights, NY and later moved to the IBM systems and Technology Group at Hopewell Junction, NY where he was appointed IBM Fellow and was till recently Director of the Systems Scaling Technology Department. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical Fuses, embedded DRAM and 45nm technology used at IBM and IBM’s development partners to make the first generation smartphone devices and more recently developing commercial 3D die stacking processes used in the Hybrid Memory Cube and Silicon Interposer products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 300 papers and holds over 70 patents. At UCLA he is pioneering the development of new ways for heterogeneous integration. His current technical interests and work lie in the area of advanced packaging and three-dimensional integration for system-level scaling and new integration and computing paradigms as well as the long-term semiconductor and packaging roadmap for logic, memory and other devices including hardware security and supply-chain integrity. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow and a Distinguished Lecturer of the IEEE EDS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012. He also studies Sanskrit in his spare time.

 

He served as secretary of the IEEE student Chapter at IIT Bombay (‘75-‘76). He has served two terms on the EDS BoG (2009-2015) and currently is EDS Treasurer. He has served as the Chairman of the IEEE Mid-Hudson EDS chapter (2007-2008). He serves as a non-voting member of the CPMT BoG and is the EDS-CPMT liaison volunteer. He also serves on an ad-hoc committee on rebranding the CPMT and serves on the steering committee of the Heterogeneous Integration Roadmap committee sponsored by CPMT and other societies and SEMI. He mentors at the local IEEE student chapters. He has served on the Fellows’ committee for EDS and IEEE. He is also a member of the APS.