Bio Poupon

GILLES POUPON (M’05-SM’10) currently holds the position of International Expert on Advanced Packaging and 3D Integration at CEA-LETI in Grenoble (France). He has an extensive experience in technologies relating to smart system packaging, 3D integration and heterogeneous integration technologies (SiP, Wafer Level Packaging, Flip-Chip, Fine Pitch Interconnection, Solder Bumping, Thermal Management, Packaging for Microsystems and MEMS). In the course of his involvement in packaging, he has worked on specific technologies based on wafer level processes, Fan-Out WLP, fine pitch & high density interconnections, TSV processes, direct bonding, micro-cooling).
 
He received his formal education at University of Grenoble and Conservatoire National des Arts et Métiers in Paris. He received his M.S. in Electrochemistry in 1985. He joined CEA-LETI in 1987. Since 2004, Gilles was Director of Strategic Programs on Advanced Packaging at CEA-LETI. Subsequently, he became the Head of the High Density Interconnection and Packaging Laboratory at LETI.
 
Gilles Poupon is active in electronic packaging since 2001. He is Senior Member of IEEE (SM’10) and Chair of IEEE-CPMT French chapter since 2014. He has worked in establishing the IEEE workshops in France and he has been active on the technical committees for ECTC and ESTC. He is the General chair of ESTC 2016 in Grenoble, France. Additionally, he is the Technical Director of the French chapter of IMAPS since 2006 and involved in the technical committee of IMAPS events. He was the Technical Chair of conference EMPC 2013.
 
Gilles Poupon is a Scientific Advisor of EURIPIDES (European cluster on packaging) and committee member of Smart System Integration Conference and Semicon Europa – Advanced Packaging Conference. He is also a member of IEEE-CPMT Heterogeneous Integration Technology Roadmap Working Group (previously ITRS Assembly & Packaging Technical Working Group), iNEMI and ESIPAT (European SEMI integrated Packaging Assembly and Test group). He has published two books (Hermes Science; 2008 and 2011) on advanced packaging and new processes for interconnections. He has authored several chapters of books and co-authored and authored over 60 proceedings papers, review and journal papers. He has more than 10 patents in the field of advanced packaging, micro systems technologies and 3D integration.
 
Since 2012 he served as a Member at Large Region 8 of the CPMT Board of Governors. During this term on the BoG he promoted IEEE EPS in Europe (workshop organizations, conferences, exhibitions,…) and he has participated on membership development. He has been requested by the IEEE EPS board to organize ESTC 2016 conference in Grenoble. This event has been meticulously and attentively prepared in collaboration with all of the CPMT European chapters.