EPS Webinar Archive
Understanding Voids in Flip Chip Interconnects
- Webinar - Online
- Marsha Tickman – firstname.lastname@example.org
- Eric Perfecto
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Presenter: Eric Perfecto
Pb-free solder is now ubiquitous throughout the packaging industry. Pb-freesolder interconnects dominate the high-end packaging interconnects: from large ball grid array (BGA) used on organic laminate to board connections, to flip chip joints on laminates, to micro-pillar forchipto Si on 2.5D or 3D interconnects But, how robust are these connections? Which defects are common and which can be avoided? This talk will cover one of the more common interconnect defects: solder voids. It will explain the root cause of solder voids occurring during structure fabrication, assembly and reliability stress, as well as detection methods and possible actions to prevent them.
Eric Perfecto has 36 years of experience working in microelectronics. First at IBM working in the development of multi-level Cu-polyimide advanced packages for high-end systems, followed by the development of the UBM and Pb-free solder processes and yields for flip chip in 2D and 3D packages. As part of the IBM Microelectronics Division divestiture, Eric is now a PMTS at GLOBALFOUNDRIES. His technical interests include 3D interconnects, chip-package interaction, electromigration, Silicon photonics and design for manufacturing. He holds a M.S. in Chemical Engineering from the University of Illinois and a M.S. in Operations Research from Union College.
An author of more than 75 technical papers and two book chapters, Eric received two Best Conference Paper Awards (2006 ESTC and 2008 ICEPT-HDP) and the 1994 Prize Paper Award from CPMT Trans. on Adv. Packaging. He holds 55 US patents and has been honored with two IBM Outstanding Technical Achievement Awards: one for the development and implementation of Cu-Polyimide structures, and the other for the development and implementation of 150 um pitch Pb-Free C4 technology; and an IBM Outstanding Contribution Award for the development of 3D wafer finishing process (2014). He is a participating member of SRC.