EPS Webinar Archive
Flip Chip Interconnection and Its Application
- 1:00 PM EDT
- Webinar - Online
- Denise Manning – email@example.com
- Dr. Shengmin Wen
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This webinar will cover the fundamentals of all steps and aspects of flip chip integration in semiconductor packaging, including wafer bumping, solder joint formation processes, underfill types, substrate selection, and reliability evaluation. It also included a small portion of discussion on how to select a package to achieve a reliable, innovative, better time to market, and more cost-effective solution. The targeted audience includes anyone who wants a basic understanding of flip chip integrations: the advantages, limitations and how to apply.
Dr. Shengmin Wen is the Principal Development Engineer at Synaptics Inc., has 20 years of semiconductor industry experience in the areas of Si fabrication technology, advanced packaging and assembly process development, Si and packaging co-design, semiconductor device failure analysis, reliability and qualification, product engineering, testing, and volume production business management. Recent years, he focused on chip scale package (CSP) including wirebond, flipchip, wafer level Fan-In and Fan-out, and panel level packaging development. In particular, he has extensive and unique experiences in flip chip assembly technologies that uses fine pitch Cu Pillar bump with both mass reflow and thermal compression processes. He is an expert in package warpage control, substrate technologies, and advanced fine pitch flip chip assembly process. He previously worked at Amkor Technology where he was a director of 3D CSP Product Group. Dr. Wen received his Ph.D. in Theoretical and Applied Mechanics from Northwestern University, Evanston, IL, USA, researching on fatigue and reliability of electronic materials, where he created and published a science based fatigue theory. Dr. Wen has been actively participating and contributing to industry technical conferences to learn, to share, and to contribute.
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