EPS Webinar Archive
TSV and FOWLP Reliability Challenge Overview
- 11:00 AM EST
- Webinar - Online
- Denise Manning – email@example.com
- Darvin Edwards
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Abstract: Through Silicon Via (TSV) and Fan Out Wafer Level Packages (FOWLP) are two of the most rapidly growing package technologies in today’s semiconductor industry. These package technologies borrow from past packaging processes with many novel additional improvements and refinements to meet the new application needs. New or refined wafer fab and package processes include deep TSV drilling, TSV plating, wafer thinning, backside interconnect fabrication, thermo-compression Cu pillar bonding, capillary and molded underfilling, over molding, temporary carrier attach, and thin die pick-and-place among many others. As with any new package technology, reliability risks must be evaluated with special emphasis on failure mechanisms that might arise from the new package configurations and applications. The package design and process development engineer must understand the factors that play into new technology reliability failure mechanisms, as well as mitigations that can be employed to ensure that highly reliable products can be produced. Without this knowledge, reliability failures are bound to occur.
This webinar will briefly review current predominant fabrication processes for both TSVs and FOWLPs. Major TSV reliability risks such as Cu pumping, side wall dielectric cracking, Back-End-of-Line (BEOL) cracking, underfill voids, wafer backside contamination, and thermal issues will be addressed with multiple solutions provided. The FOWLP discussion will highlight chip first vs. chip last issues such as chip shifting and warpage and will draw comparisons between FOWLP board level thermal cycling and drop reliability vs. FCBGAs and WLCSPs. Example finite element modeling and experimental studies will be presented to illustrate the steps that must be taken to insure reliability has been designed in as the package processes are being developed.
Bio: Mr. Darvin Edwards has 38 years of experience in the IC packaging industry. He is currently owner of Edwards’ Enterprise Consulting LLC which specializes in helping companies solve package reliability problems, assisting in rapid product development, as well as providing worldwide training on topics such as package reliability, materials, TSV and FOWLP technologies, package design and surface mount techniques. Previously, he worked 14 years as a Fellow at Texas Instruments, managing the Dallas electrical, thermal and thermomechanical modeling team responsible for chip-package interactions and reliability of multiple TI product lines. He has served the IEEE EPS as Member at Large and is the co-chair of the Electronics Components and Technology Conference Applied Reliability committee. Mr. Edwards has authored and co-authored over 65 papers and articles in the field of IC packaging, has written two book chapters, and holds 24 US patents. He is an IEEE Senior Member.
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