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Can Moore's Law for Packaging Replace Moore's Law for ICS?

2019-02-26 - 2019-02-26
10:00 AM
Webinar - Online
Denise Manning – d.manning@ieee.org
Prof. Rao Tummala

Abstract: This webinar proposes Moore’s Law for Packaging to replace Moore’s Law for ICs, as this is seen as coming to an end. Moore’s Law for ICs is about scaling transistors to ever smaller sizes, from node to node and interconnecting and integrating these to result in more transistors in smaller chips at lower cost from 300 mm wafers. As transistor scaling and integration comes to an end due to physical, material and electrical limitations, Moore’s Law for Packaging (MLP) can be viewed as interconnecting and integrating smaller chips with the highest transistor density and highest performance at the lowest cost. Package or system scaling is proposed to be one and the same, as the end goal of packaging is a system. Just as Moore’s Law for ICs has two components: number of transistors and cost of each transistor, Moore’s Law for Packaging is proposed to have two components as well: the number of interconnections or I/Os and the cost of each I/O. This  webinar lays the ground work for Moore’s Law for Packaging by showing how I/Os have evolved from one package family node to the next, starting with <16 I/Os in 1960s to the current silicon interposers with about 200,000 I/Os. It proposes a variety of ways to extend Moore’s Law such as extending Si interposers and beyond, using glass in panel embedding. As Moore’s Law for Electronic Packaging comes to its own end, this article proposes 3D opto-electronic packaging as the next Moore’s Law for Packaging.

Currently, the most advanced Moore’s Law for Packaging is with wafer-based silicon packaging. But silicon-based packaging has many limitations at material, substrate or interconnect and system levels. At material level, its electrical loss and its dielectric constant are very high. At interconnect level, its capacitance and resistance are very high, leading to so-called RC delays. In addition, Si-based packaging doesn’t conform to Moore’s Law for cost. Cost, of course, is the basis for going away from Moore’s Law for ICs. At system levels, Si interposers, while they are perfectly matched to ICs, they are totally mismatched to boards, requiring additional packaging, thus making system level interconnections even longer. 
So what are future technologies beyond Si interposers to drive Moore’s Law for  Packaging.This course will present and discuss a variety of options.Bio: 
Prof. Rao Tummala is a Distinguished and Endowed Chair Professor Emeritus at Georgia Tech in USA. He is well known as an industrial technologist, technology pioneer, and educator. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering such major technologies as the industry’s first plasma display and industry’ first  100- chip MCM with leading-edge  RDL, flipchip and liquid cooling, now called 2.5D. He is the father of LTCC and System-on-Package(SOP) technologies. As an educator, Prof. Tummala was instrumental in setting up the largest and most comprehensive Academic Center in System-On-Package  vision for Electronic Systems, funded by NSF as the first and only NSF Engineering Research Center in US in Packaging at Georgia Tech. Prof. Tummala pioneered an integrated approach to research, education and industry  collaborations with  more than 100 companies in US, Europe, Japan, Korea, Taiwan and China and producing about 1200 Ph.D and MS students . He received many industry, Academic and Professional Society awards including Distinguished Alumni of Illinois, Indian Institute of Science and the highest Faculty award from Georgia Tech—The Distinguished Faculty. He has published about 800 technical papers and invented many technologies that resulted in over 100 patents. He wrote the first modern textbook in packaging, Microelectronics Packaging Handbook(1988); wrote the 1st undergrad textbook, Fundamentals of Microsystem Packaging(2001); and the 1st  book introducing the concept of SOP with Prof. Swaminathan, Introduction to System-on-Package( 2006). He was  Past President of IEEE EPS and IMAPS. He is an IEEE Fellow and  member of National Academy of Engineering in  US.

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