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Interconnects for 2D and 3D Architectures

2020-05-13 - 2020-05-13
11:00 AM EDT
Webinar - Online
Denise A Manning – d.manning@ieee.org
Ravi Mahajan

With increasing interest in on-package integration, there is a need to describe package architectures and their interconnect capabilities in a simple and consistent manner.  This webinar has two primary objectives: to (a) define and proliferate a new standardized nomenclature for package architectures covering and clearly demarcating both 2D and 3D constructions and to (b) define and proliferate key metrics driving the evolution of the physical interconnects in these architectures.  The webinar will focus on describing envelopes for how package interconnects should scale to support increasing on-package bandwidth requirements.  The webinar will also touch upon the scaling of key metrics to ensure efficient power delivery and low loss high speed signaling.


Brief bio

Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi joined Intel in 1992 after earning Ph.D. in Mechanical Engineering from Lehigh University.  He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have also led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques used for thermo-mechanical stress model validation. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT.  He is an IEEE EPS Distinguished Lecturer.  His contributions during his Intel career have earned him numerous industry honors, including most recently the 2020 Richard Chu ITHERM Award for Excellence He has been long associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference.  Ravi is aFellow of two leading societies, ASME and IEEE.  He was named Intel Fellow in 2017. 


Download HIR Chapter 22  Interconnects for 2D and 3D Architectures

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