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Overview of the High-Performance Computing Chapter of the Heterogeneous Integration Roadmap

Date
2020-06-18 - 2020-06-18
Time
11:00 AM EDT
Location
Webinar - Online
Contact
Denise Manning – d.manning@ieee.org
Sponsorship
Sponsor
Presenter
Dr. Dale Becker and Prof. Kanad Ghose
Description

Abstract

The High Performance Computing and Data Center chapter of the Heterogeneous Integration Roadmap presents the clear need for heterogeneous system integration that realizes systems-in-a-package (SiPs) that target the HPC and data center markets. The potential solutions and short-term, medium-term and longer-term challenges that are encountered in realizing these SiPs are addressed. Although, as in the past, the processor-memory performance gap remains a key driver for the overall system architecture, new factors that drive the need for heterogeneous integration in the HPC and data center markets have been emerging. These factors include technology limitations, new and emerging applications, and scaling needs for surmounting power dissipation, power delivery and package IO constraints.

 

Bio

Dale Becker received a Ph.D. in Electrical Engineering from UIUC. He is a Chief Engineer of Electronic Packaging Integration in IBM Systems. His responsibility is the electrical system packaging architecture of IBM Systems including the design of high-speed channels to enable the computer system performance and the power distribution networks for reliable operation of the integrated circuits that make up the processor subsystem.

Dr. Becker has chaired the IEEE EPEPS Conference and the SIPI Embedded Conference of the EMC Symposium. He currently chairs the IEEE EPS Technical Committee on Electrical Modeling, Design, and Simulation and is a Senior Area Editor for the Transactions on CPMT. Dale co-chairs the High-Performance Computing TWG of the HIR Roadmap. From 2017-2018, he was the IAB chair for NSF U/ICRC Center on Advancing Electronics through Machine Learning (CAEML). He has chaired the iNEMI PEG on High-End Systems including the chapter on the High-End Systems Roadmap from 2007 to 2017. He is an IEEE Fellow, an iNEMI Technical Committee member, and a member of SWE.

 

Kanad Ghose received the PhD degree from Iowa State University. He is currently a Distinguished Professor with the Computer Science Department, State University of New York, Binghamton, where he served as the Department Chair from 1998 to 2016. His research work has been funded by the NSF, DARPA, AFOSR as well as the industry (Intel, IBM, Lockheed-Martin, BAE Systems, SRC, NBMC, etc.). His current research interests include power-aware microarchitecture and systems ranging from ultra low-power sensors to high-performance processors and data centers. He has authored technical papers extensively in these areas. He holds 25 awarded patents, including four licensed patents. Kanad is a Fellow of the National Academy of Inventors and a member of the IEEE and ACM. He serves as the Site Director for the Center for Energy-Smart Electronics Systems, a Phase II NSF Industry-University Cooperative Research Center at Binghamton, the founding site, with three other university sites. He is co-chair of the HI Roadmap’s Working Group on HPC and Data Centers.

Download HIR Chapter 2 High Performance Computing and Data Centers

Event Recording
View Overview of the High-Performance Computing Chapter of the Heterogeneous Integration Roadmap recording