EPS Webinars

Attend lectures on the latest technology development topics within the EPS’s scope, presented by experts in our field -- through EPS Webinars.  No travel required.

Available to EPS Members only -- as a Member benefit, with no cost to you.

Recordings of and/or presentations from past Webinars can be accessed by EPS Members in the EPS Webinar Archive.

Earn 1 Professional Development Hour (PDH) for completing an EPS webinar - Complete Form



Heterogeneous Integration Roadmap (HIR) Webinar Series (OPEN TO EVERYONE AT NO COST)

The electronics industry has reinvented itself through multiple disruptive changes in technologies, products, applications and markets. Our industry continues to evolve with the rapid migration of logic, memory, and applications to the cloud, the evolution of the Internet of Things (IoT) to the Internet of Everything (IoE), the proliferation of smart mobile devices everywhere, the rise of 5G, the increasing presence of microelectronics in wearables,  health applications, and  the rapidly evolving issues related to autonomous vehicles applications. Underlying all the changes are the rapid advancement of AI and the increasing abundance of data & data analytics.  The pace of innovation is  increasing to meet these challenges.

The Heterogeneous Integration Roadmap (HIR), released October 2019, is a roadmap to the future of electronics identifying technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration between industry, academia and government to accelerate progress. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of Emerging Research Devices and Emerging Research Materials with longer research-and-development timelines. With the release of the 2019 HIR edition, the preparation of the 2020 edition is underway.

We are announcing the Heterogeneous Integration Webinar Series. The series is based upon the content of the 2019 HIR edition. The webinars will be delivered by the authors of the individual roadmap chapters. The primary purposes are to broaden the proliferation of the roadmap content to the profession and industry and to seek feedback from the roadmap users for inclusion into the 2020 edition.

Watch for the invitation or visit this website for schedule details and instructions about how to register. 

Download the 2019 Edition of the HIR

Upcoming Webinars

Title: Thermal Management Challenges and Opportunities for Heterogeneous Packages

Date: May 27, 2020

Time: 11:00 AM EDT - Register Here

Presenter: Dr. Madhu Iyengar and Mehdi Asheghi

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In response to a growing awareness of thermal challenges related to Heterogeneously Integrated Packages, a Thermal Technical Working Group has focused on trends for cooling requirements, known technical solutions, and advanced concepts and research covering three areas, namely, the die level, the package integration/SIP/module level, and to a lesser extent the system Level (limited to board level). This webinar covers two primary thermal aspects related to heterogeneous integration: (a) definition of canonical problems and thermal challenges, and (b) active research areas and results, which have been the focus of the published 2019 roadmap chapter.  The canonical problems have included: 2D chip with stacked memory on a silicon/glass interpose, 3D stacked die with conduction interfaces, 3D stacked die with embedded liquid cooling, optics/photonics cooling, thermal management for harsh environment (military, aerospace, automobile), mobile applications, and voltage Regulators. The research and advance cooling advances encompass Thermal Interface Materials, liquid cooling, single and two-phase liquid cooling, air cooling, materials, and modeling. The talk will also touch upon an ongoing effort for the 2020 chapter related to recent roadmap discussions around memory cooling, silicon micro-channels, and photonics cooling.


Madhu Iyengar is a Senior Staff Engineer at Google and a lead with technical and managerial responsibilities for innovative product development and path-finding for IT hardware and physical infrastructure, including chip packages, server systems, and data centers.  As Chief Engineer since 2015, he has led Google’s chip-to-data center liquid cooling research and product development program, yielding the delivery of a breakthrough liquid-cooled high performance Machine Learning IT System that has been globally deployed at scale.  Previously, he has worked at Facebook, IBM, Purdue University's Cooling Technology Research Center, and Kirloskar Oil Engines.  He has a PhD in Mechanical Engineering from the University of Minnesota.  Madhu has served as an Associate Editor for the ASME Journal of Electronic Packaging, the IEEE CPMT Transactions and the ElectronicsCooling Magazine, a voting member of the ASHRAE TC9.9 Mission Critical Facilities committee, and as the General Chair of the 2016 ITherm Conference.  He has co-authored over 115 technical papers in journals, conference proceedings and book chapters, edited 1 book, and holds 280 US patents.  He is currently the Chair for the Thermal Technical Working Group for the IEEE Electronics Packaging Society Roadmap effort on Heterogeneous Integration.  Madhu is an elected Fellow of the American Society of Mechanical Engineers.  His contact is miyengar@google.com.

Adjunct Professor Mehdi Asheghi was a founding member of the Stanford Nanoheat Laboratory as a graduate student back in 1994.  He completed his Ph.D. and postdoctoral studies at Stanford through research on nanoscale thermal engineering of microelectronic devices, including several highly cited papers on phonon conduction in silicon layers. He led a very well funded research program at Carnegie Mellon University (2000-2006) that focused on nanoscale thermal phenomena in semiconductor and data storage devices. At Stanford his research ranges from nanoscale memory technologies to two phase microfluidics.  Dr. Asheghi is the author of more than 200 journal publications,fully-reviewed conference papers, and book chapters, and was technical program and  general chairs at ITHERM 2012, 2014 and InterPACK 2015 and 2017, respectively.  Mehdi is a member of theThermal Technical Working Group (TWG) of the IEEE EPS HIR initiative.

Download HIR Chapter 20 Thermal


Title: Overview of the High-Performance Computing Chapter of the Heterogeneous Integration Roadmap

Date: June 18, 2020

Time: 11:00 AM EDT - Register Here

Presenter: Dr. Dale Becker and Prof. Kanad Ghose

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The High Performance Computing and Data Center chapter of the Heterogeneous Integration Roadmap presents the clear need for heterogeneous system integration that realizes systems-in-a-package (SiPs) that target the HPC and data center markets. The potential solutions and short-term, medium-term and longer-term challenges that are encountered in realizing these SiPs are addressed. Although, as in the past, the processor-memory performance gap remains a key driver for the overall system architecture, new factors that drive the need for heterogeneous integration in the HPC and data center markets have been emerging. These factors include technology limitations, new and emerging applications, and scaling needs for surmounting power dissipation, power delivery and package IO constraints. 


Dale Becker received a Ph.D. in Electrical Engineering from UIUC. He is a Chief Engineer of Electronic Packaging Integration in IBM Systems. His responsibility is the electrical system packaging architecture of IBM Systems including the design of high-speed channels to enable the computer system performance and the power distribution networks for reliable operation of the integrated circuits that make up the processor subsystem.

Dr. Becker has chaired the IEEE EPEPS Conference and the SIPI Embedded Conference of the EMC Symposium. He currently chairs the IEEE EPS Technical Committee on Electrical Modeling, Design, and Simulation and is a Senior Area Editor for the Transactions on CPMT. Dale co-chairs the High-Performance Computing TWG of the HIR Roadmap. From 2017-2018, he was the IAB chair for NSF U/ICRC Center on Advancing Electronics through Machine Learning (CAEML). He has chaired the iNEMI PEG on High-End Systems including the chapter on the High-End Systems Roadmap from 2007 to 2017. He is an IEEE Fellow, an iNEMI Technical Committee member, and a member of SWE.

Kanad Ghose received the PhD degree from Iowa State University. He is currently a Distinguished Professor with the Computer Science Department, State University of New York, Binghamton, where he served as the Department Chair from 1998 to 2016. His research work has been funded by the NSF, DARPA, AFOSR as well as the industry (Intel, IBM, Lockheed-Martin, BAE Systems, SRC, NBMC, etc.). His current research interests include power-aware microarchitecture and systems ranging from ultra low-power sensors to high-performance processors and data centers. He has authored technical papers extensively in these areas. He holds 25 awarded patents, including four licensed patents. Kanad is a Fellow of the National Academy of Inventors and a member of the IEEE and ACM. He serves as the Site Director for the Center for Energy-Smart Electronics Systems, a Phase II NSF Industry-University Cooperative Research Center at Binghamton, the founding site, with three other university sites. He is co-chair of the HI Roadmap’s Working Group on HPC and Data Centers.

Download HIR Chapter 2 High Performance Computing & Data Centers