EPS Webinars

Attend lectures on the latest technology development topics within the EPS’s scope, presented by experts in our field -- through EPS Webinars.  No travel required.

Available to EPS Members only -- as a Member benefit, with no cost to you.

Recordings of and/or presentations from past Webinars can be accessed by EPS Members in the EPS Webinar Archive.

Professional Development Hours are now available for EPS webinars

Upcoming Webinars

Title: Achieving High Reliability for Lead-Free Solder Joints - Materials Consideration

Presenter: Dr. Ning-Cheng Lee

Date: November 20, 2018

Time: 11:00 AM EST

Register Here

Earn 1 Professional Development Hour (PDH) for completing the webinar - Complete Form

Abstract: This course covers the detailed material considerations required for achieving high reliability for lead-free solder joints. The reliability discussed includes joint mechanical properties, development of type and extent of intermetallic compounds (IMC) under a variety of material combinations and aging conditions and how those IMCs affect the reliability. The failure modes, thermal cycling reliability, and fragility of solder joints as a function of material combination, thermal history, and stress history will be addressed in details, and novel alloys with high reliability will be presented.  The emphasis of this course is placed on the understanding of how the various factors contributing to the failure modes, and how to select proper solder alloys and surface finishes for achieving high reliability.

 Bio: Ning-Cheng Lee is the Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 30 years of experience in the development of fluxes and solder pastes for SMT industries. In addition, he also has very extensive experience in the development of underfills and adhesives. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973.

Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies” by Newnes, and co-author of “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials” by McGraw-Hill. He is also the author of book chapters for several lead-free soldering books. He received 1991 award from SMT Magazine and 1993 and 2001 awards for best proceedings papers of SMI or SMTA International Conferences, 2008 and 2014 awards from IPC for Honorable Mention Paper – USA Award of APEX conference, and 2010 Best Paper Award of SMTA China South Conference.  He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 IEEE Senior Member, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow. He has served on the board of governors for CPMT and SMTA board of directors. Among other editorial responsibilities, he serves as editorial advisory board of Soldering and Surface Mount Technology, Global SMT & Packaging and as associate editor for IEEE Transactions on Components Packaging Manufacturing Technology.  He has numerous publications and frequently gives presentations, invited to seminars, keynote speeches and short courses worldwide on those subjects at international conferences and symposiums. 


Title: TSV and FOWLP Reliability Challenge Overview

Presenter: Darvin Edwards

Date: November 29, 2018

Time: 11:00 AM EST

Register Here 

Earn 1 Professional Development Hour (PDH) for completing the webinar - Complete Form

Abstract:  Through Silicon Via (TSV) and Fan Out Wafer Level Packages (FOWLP) are two of the most rapidly growing package technologies in today’s semiconductor industry.  These package technologies borrow from past packaging processes with many novel additional improvements and refinements to meet the new application needs.  New or refined wafer fab and package processes include deep TSV drilling, TSV plating, wafer thinning, backside interconnect fabrication, thermo-compression Cu pillar bonding, capillary and molded underfilling, over molding, temporary carrier attach, and thin die pick-and-place among many others.  As with any new package technology, reliability risks must be evaluated with special emphasis on failure mechanisms that might arise from the new package configurations and applications.  The package design and process development engineer must understand the factors that play into new technology reliability failure mechanisms, as well as mitigations that can be employed to ensure that highly reliable products can be produced.  Without this knowledge, reliability failures are bound to occur.

This webinar will briefly review current predominant fabrication processes for both TSVs and FOWLPs.  Major TSV reliability risks such as Cu pumping, side wall dielectric cracking, Back-End-of-Line (BEOL) cracking, underfill voids, wafer backside contamination, and thermal issues will be addressed with multiple solutions provided.  The FOWLP discussion will highlight chip first vs. chip last issues such as chip shifting and warpage and will draw comparisons between FOWLP board level thermal cycling and drop reliability vs. FCBGAs and WLCSPs.  Example finite element modeling and experimental studies will be presented to illustrate the steps that must be taken to insure reliability has been designed in as the package processes are being developed. 

Bio: Mr. Darvin Edwards has 38 years of experience in the IC packaging industry.  He is currently owner of Edwards’ Enterprise Consulting LLC which specializes in helping companies solve package reliability problems, assisting in rapid product development, as well as providing worldwide training on topics such as package reliability, materials, TSV and FOWLP technologies, package design and surface mount techniques.  Previously, he worked 14 years as a Fellow at Texas Instruments, managing the Dallas electrical, thermal and thermomechanical modeling team responsible for chip-package interactions and reliability of multiple TI product lines.  He has served the IEEE EPS as Member at Large and is the co-chair of the Electronics Components and Technology Conference Applied Reliability committee.  Mr. Edwards has authored and co-authored over 65 papers and articles in the field of IC packaging, has written two book chapters, and holds 24 US patents.  He is an IEEE Senior Member.