Members Only: Thin is In (July 2012)

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IEEE/CPMT Workshop in: Thin Is In: Thin Chip & Packaging Technologies as Enabler for
Innovative Mobile Devices

Tuesday, July 10, 2012 at SEMICON West 2012

Electronic products, such as smart phones, tablets and other consumer products drive the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs. Here, thin 3D-packaging is one of the key Technologies to achieve these goals. Developments have lately been made with various embedding technologies, such as Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes at which most R&D is concentrated in the commercialization of 2.5D IC´s (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.

In this workshop, leaders from key segments of the eco-system shared their perspectives and experiences on the readiness for commercialization and what the future directions and opportunities in this emerging area of “Thin Packaging Technology.

Session Co-chairs:

Rolf Aschenbrenner, Fraunhofer IZM, Berlin and  Jie Xue, Cisco


(Click on title to view presentation)

  • eWLBTM Wafer-level Fan-out Technology – A New Package Platform for High Performance and Small Form Factor Packaging, Rajendra D. Pendse, STATSChipPAC, Inc.(this presentation is not available)