Date: Thursday, February 22, 2018

Time: 8:30 AM to 5:30 PM

Register: $40 IEEE members. students, unemployed, $50 non-members ($10 more, after Feb 9th)

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara, CA 

Program

·       Presentations from HIR Technical Working Group chairs

·       Overview from HIR International Roadmap Committee

We are entering the era of the digital economy and myriad connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.

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·         A Filtering Dual-Polarized Antenna Subarray Targeting for Base Stations in Millimeter-Wave 5G Wireless Communications

Hui Chu ; Yong-Xin Guo

Publication Year: 2017, Page(s):964 - 973

Manufacturing Considerations in the 3-D Printing of Fractal Antennas

Multi-Die Heterogeneous Integration: Design Considerations and Technology Demonstrations

Wednesday January 31, 2018 11:00 AM EST

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Presenter: Muhannad Bakir

Abstract: 

This presentation will discuss high-density multi-die integration approaches both in 2.5D and 3D, though we will emphasize 2.5D architectures. Specifically, we first discuss various 2.5D approaching including Heterogeneous Interconnect Stitching Technology (HIST), which enables the interconnection of multiple dice of various functionalities in a manner that mimics monolithic-like performance, yet utilizes advanced off-chip interconnects and packaging to provide flexibility in IC fabrication and design, improved scalability, reduced development time, and reduced cost. A key feature of HIST is the ability to place a 'stitch chip' between adjacent ICs on the surface of an organic/ceramic package and use multi-height I/Os to interface the active dice to the package and stitch chips simultaneously. Design considerations and benchmarking (power delivery, signaling, and thermal) will be described and experimental demonstrations will be shown. Secondly, we discuss highly-scaled 3D ICs using sub-micron TSVs and report fabrication and characterization results; we also discuss the impact of TSV geometry on 3D end-to-end interconnect links (energy and latency) accounting on-chip wire resistance and capacitance. Third, and lastly, we briefly discuss 3D IC applications in CMOS multimodal biosensors.

Bio:
Muhannad S. Bakir is a Professor in the School of Electrical and Computer Engineering at Georgia Tech. Dr. Bakir and his research group have received more than twenty five conference and student paper awards including six from the IEEE Electronic Components and Technology Conference (ECTC), four from the IEEE International Interconnect Technology Conference (IITC), and one from the IEEE Custom Integrated Circuits Conference (CICC). Dr. Bakir’s group was awarded the 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology in the area of advanced packaging.

Dr. Bakir is Editor-in-Chief of the IEEE Transactions on Components, Packaging and Manufacturing Technology, Manufacturing Section and Editor of IEEE Transactions on Electron Devices.