EP Section within IEEE Access
We invite you to be among the first to have your article peer-reviewed and published in the new Electronics Packaging section within IEEE Access. This is an exciting opportunity for your research to benefit from the high visibility of IEEE Access. Your work will also be exposed to 5 million unique monthly users of the IEEE Xplore® Digital Library.
The Electronics Packaging Section within IEEE Access will draw on the expert technical community to continue IEEE’s commitment to publishing the most highly-cited content. The Journal peer-review process targets a publication period of 6 weeks for most acceptecd papers. This journal is fully open and compliant with funder mandates, including Plan S.
Scope
The IEEE Electronics Packaging Society section in IEEE Access covers the scientific, engineering, and production aspects of materials, components, modules, hybrids and micro-electronic systems for all electronic applications, which includes technology, selection, modeling/simulation, characterization, assembly, interconnection, packaging, handling, thermal management, reliability, testing/control of the above as applied in design and manufacturing. Examples include optoelectronics and bioelectronic systems packaging, and adaptation for operation in severe/harsh environments. Emphasis is on research, analysis, development, application and manufacturing technology that advance state-of-the-art within this scope.
EuroSimE 2020
EuroSimE 2020 Cracow is postponed to Sunday July 05th to Wednesday 08th.
Considering the fact that many people are unable to travel for an unknown period of time, because of corporate directives, the EuroSimE Steering Committee decided to postpone the event to July 5th-8th. As a results, the deadlines for registration are shifted as well. On top of that, we also allow for submission of new abstracts.
Speakers: the deadline for you to register and post final papers is now May 31. It is possible to submit new abstracts until May 08.
Follow www.eurosime.org for updates on the conference.
Technical Committee (TC) – Electrical Design, Modeling, and Simulation (EDMS)
The Electrical Design, Modeling, and Simulation technical committee of the Electronics Packaging Society (EPS) addresses the electrical aspects of package and system design. The TC name is descriptive of the scope of issues of interest to the members. The committee strives to balance the industry and academic participation to guide the members of the EPS society in this area. The TC chairs are Dr. Dale Becker, IBM, Prof. Stefano Grivet-Talocia, Politecnico di Torino, and Prof. Rohit Sharma, IIT Ropar.
Recently, EDMS has initiated a joint industry – academic effort to establish a “Package Benchmark Suite.” This effort is chaired by Dr. Fei Guo of AMD and Prof. Ali Yilmaz of UT-Austin and has about 15 active participants. Initial package designs are nearing availability through this effort to represent signal distribution and power distribution. Dr. Kemal Aygun presented a detailed overview of this effort as a session and led a productive planning meeting in October 2019 at the EPEPS conference in Montreal.
IEEE EPS Seminar at ECTC 2020
ECTC 2020 IEEE EPS Seminar: May 28, 2020
Chair
Yasumitsu Orii, NAGASE & CO., LTD.
Shigenori Aoki, LINTEC Corporation
“Future Semiconductor Packages for AI hardware”
An overwhelming amount of data is generated daily, out which 90% is unstructured. Such data cannot be easily stored in a traditional column-row database, therefore, it is not easily searchable and more difficult to analyze. Today, artificial intelligence (AI) has the ability to analyze unstructured data, however, it also require a high amount of energy. AI is expected to become one of the biggest energy consumers on the planet. A brain-inspired devices and quantum devices are very attractive to support a future AI due to its low power consumption. In this session, the panelists will discuss the future semiconductor packages in the era of a brain-inspired devices and quantum devices.
Rama Divakaruni, IBM T. J. Watson Research-Albany, “Future of Innovation - IBM AI Hardware Center”
Hiroyuki Akinaga, The National Institute of Advanced Industrial Science and Technology (AIST), “Brain-inspired ReRAM Devices for AI-edge Computing”
Subramanian S. Iyer, UCLA, “Why all this hype about Heterogeneous Integration ?”
Takashi Hisada, IBM Research-Tokyo, “Heterogeneous Integration for IBM AI Hardware”
Madhavan Swaminathan, Georgia Institute of Technology, ”Intelligent Digital and RF Convergence for AI”
Most Popular T-CPMT Articles
Most Popular Articles according to Xplore® usage statistics
Muneeb Zia ; Bryce Chung ; Samuel Sober ; Muhannad S. Bakir
Publication Year: 2020, Page(s): 197 – 202
Process Modules for High-Density Interconnects in Panel-Level Packaging
Friedrich-Leonhard Schein ; Ruben Kahle ; Marc Kunz ; Tim Kunz ; Jordan Kossev ; Tobias Müller ; Mathias Pentz ; Michael Dietterle ; Andreas Ostmann
Publication Year: 2020, Page(s): 5 - 10
3-D Printed Metal-Pipe Rectangular Waveguides
Mario D’Auria ; William J. Otter ; Jonathan Hazell ; Brendan T. W. Gillatt ; Callum Long-Collins ; Nick M. Ridler ; Stepan Lucyszyn
Publication Year: 2015, Page(s): 1339 - 1349
Air Jet Impingement Cooling of Electronic Devices Using Additively Manufactured Nozzles
Beomjin Kwon ; Thomas Foulkes ; Tianyu Yang ; Nenad Miljkovic ; William P. King
Publication Year: 2020, Page(s): 220 - 229
Embedded Multidie Interconnect Bridge—A Localized, High-Density Multichip Packaging Interconnect
Publication Year: 2019, Page(s): 1952 - 1962