Heterogeneous Integration Roadmap (HIR), released October 2019, is a roadmap to the future of electronics identifying technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration between industry, academia and government to accelerate progress. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of Emerging Research Devices and Emerging Research Materials with longer research-and-development timelines. With the release of the 2019 HIR edition, the preparation of the 2020 edition is well underway.

This HIR workshop at ECTC 2020 will feature speakers from all 22 chapters in 4 separate sessions together with an HIR overview presentation. They will describe their work in HIR 2019 and their focus for HIR 2020. The purpose of the HIR workshop is to broaden the proliferation of the roadmap content to the virtual ECTC 2020 participants for dialogue and feedback for inclusion into the 2020 edition.

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Prof. Tummala of Georgia Tech publishes the most comprehensive and up–to-date Undergrad and Introductory packaging textbook, with all the Latest Device and Systems Packaging Technologies. 

Undergrad and  introductory Textbook- "Fundamentals of Device and System Packaging: Technologies and Applications” edited by Prof Tummala, published and available from Amazon and McGraw-Hill. 

For decades, Moore's Law has driven the semiconductor technology advancements.  As Moore’s Law for IC’s comes to an end due to physical, material, electrical and financial limitations, this book goes on to propose Moore’s Law for Packaging through advanced interconnections at IC and system levels. In the first chapter Prof. Tummala explains the device packaging concept and its evolution from microelectronics to  RF and wireless,  followed by photonics and MEMS and Sensors  eventually leading to quantum devices. He describes the shift in industry focus from transistors to interconnections at the system level enabled by heterogeneous integration in 2D, 2.1D, 2.5D and 3D packages. 

Prof. Tummala introduces the concept of Moore’s Law for Packaging or interconnections (MLP) that cab be viewed as interconnecting and integrating smaller chips with the highest transistor density and highest performance at the lowest cost. Just as Moore’s Law for ICs has two components -- the number of transistors and cost of each transistor -- Moore’s Law for Packaging is  proposes to have  two components as well: the number of interconnections or I/Os and the cost of each I/O. This book lays the groundwork for all the elements required to extend Moore’s Law to packaging, not only at device level but. At system level.  

This book introduces 16 essential core packaging technologies at system level. Each technology is detailed in its own chapter.  These include electrical, mechanical, and thermal design, materials and processes for electronic, photonic, wireless to 5G and to millimeter-wave, I/O interconnections and assembly to organic, Si and wafer-level packages, passive components, sealing and encapsulation, and board design and assembly.  Once these 16 building block technologies are explained, the book moves on to application of these  packaging technologies  and architectures  for autonomous driving, bioelectronics, communication systems, computer systems, flexible electronics and smartphones – dedicating a chapter to each of these applications. Nowhere else can one find a more comprehensive explanation of the fundamentals and applications of electronics packaging described in a single volume. The homework problems and recommended reading at the end of each chapter are other attributes of the book. It is the ideal undergraduate and introductory  textbook to prepare future packaging engineers, or  anyone interested in a deeper understanding of the  packaging technology. 

The book was authored and edited by Prof Rao  Tummala ,with contributions from  57 of the world’s leading experts from Intel, IBM, TI, Global Foundries, Sanmina, and many others, as well as Prof Tummala’s colleagues at Georgia Tech., UCLA, KAIST(Korea), Michigan State, Chinese Academy of Sciences, TU Dresden  and his students at Georgia Tech.

Author: Eric Perfecto

The reliability TC meet every quarter on Webex and a face to face meeting every year at ECTC conference.  The following are the major missions and visions of the reliability TC.

Identify the current reliability challenges

Advanced packaging technologies

Advanced materials/interconnects

Advanced packaging assembly processes

Package board and advanced Si BEOL/FEOL interactions

Develop the reliability roadmap on emerging technologies/devices/materials in 5 and 10 years

IC Component and System - with the HIR (Heterogeneous Integration Roadmap) Task Groups

Si – with IRDS TWGs

SiC/GaN/GaAs/InP -  with Wide Bandgap Roadmap; Ask for expert in SiC/GaN; EPOSS in Europe

Organize seminars/workshop and work with the major conferences to cover the challenging reliability issues

ECTC/IRPS/EPTC/ESTC/ICEPT/ASME Interpack/EurosimE/Itherm

The following PDCs have been conducted at EPTC 

·       EPTC2018, Advanced Integrated Circuit Design for Reliability, Dr. Richard Rao

·       EPTC2019, Reliability Mechanics and Modeling for IC Packaging - Theory, Implementation and Practices, Prof. Xuejun Fan, Lamar University

The committee has identified the following challenging reliability issues and will schedule webinars to address each of these topics.

Multi physics and multi scale interactions

Thermal, mechanical and electrical

Chip to package to board interaction mechanisms

Chip, package and system Reliability co-design/simulation

Advanced 2.5D/3D/2.x D IC and Si Photonics packages with new materials and multiple critical interfaces

GPU/CPU/FPGA with advanced Si/packaging to meet stringent automotive reliability targets

Si nodes beyond 5nm – new FET architecture/material/process/interface characterization

Reliability testing- With the silicon process and package process/material change dramatically, current JEDEC long term reliability standard need to be updated

If you are interested in joining the committee or want to know more information, please contact the following individuals.

Dr. Richard Rao, rrao@inphi.com, Reliability TC Chair, USA

Dr. Xueren Zhang, XUERENZ@xilinx.com, Reliability TC Co-Chair, Asia

Dr. Gromala Przemyslaw Jakub, PrzemyslawJakub.Gromala@de.bosch.com, Reliability TC Co-Chair, Europe