Upcoming Webinar: Test Technology for Heterogeneous Integration
Date: July 2, 2020
Time: 11:00 AM EDT - Register Here
Presenter: Dave Armstrong, Don Blair, Ken Lanier and Marc Hunter
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Abstract:
The Test Technology chapter of the HIR highlights the challenges and opportunities for the semiconductor industry as we move forward. The chapter itself is divided into 15 different white papers because of the significant diversity of different challenges the test industry must face. Whether it’s a single cell phone SIP with incredible complexity or a use-once medical sensor where incredible accuracy is life-critical the test industry must meet the needs.
With the significant recent increases in internet traffic, efficient testing of big-digital AI, server, and communications devices is more critical than ever before. Marc Hutner will discuss how logic test is confronting this challenge, including a discussion on how design-for-test (DFT) is both challenging and helping the industry as we move forward.
The roll out of 5G mobile phone devices is anticipated to be a world-changing advancement. Meeting this need requires many advancements in the test technology of RF devices. Don Blair will provide an overview of how the test industry is changing in order to meet these challenges.
It is really difficult for the industry to maintain a cost-effective test cost when device complexity is growing in so rapidly and in so many directions. The number of transistors per piece of silicon continues to grow. The number of die per package now accelerates this transistor growth exponentially. Additionally, test must evolve in very many different domains, some quite new and difficult; (Logic, RF, Photonic, Memory, Thermal, Sensors, Analog, Reliability, 3D, System Level, Automotive, Quantum, Medical, etc.) All this does make it difficult to keep the cost-of-test from skyrocketing. Ken Lanier will discuss steps the industry is taking to meet these challenges and what the results and forecast is for device test costs.
Upcoming Webinar: Overview of the Modeling & Simulation Chapter of the Heterogeneous Integration Roadmap
Date: July 8, 2020
Time: 11:00 AM EDT - Register Here
Presenter: Professor Chris Bailey and Professor Xuejun Fan
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Abstract
The Modeling and Simulation Chapter of the Heterogeneous Integration Roadmap presents the clear need for modelling & simulation to support co-design across the die-package-board-system domains. At present electrical, thermal, and mechanical analysis is mainly undertaken separately with electrical and recently thermal analysis undertaken for chip-design, and electrical, thermal, and mechanical analysis undertaken at the package/board and system levels by different design teams, generally using different tools. The future is a more integrated and collaborative approach, using multi-physics and machine learning tools, to address issues such as signal/power integrity, thermal management, and reliability. This webinar will detail the current state-of-the-art, challenges (such as chip-package interactions), and potential solutions to these. Several examples will be demonstrated detailing progress in modelling, simulation and characterization methodologies for multi-physics and multi-scale analysis.
Bio
Chris Baileyis President of the IEEE Electronics Packaging Society and Director of the Computational Mechanics and Reliability Group at the University of Greenwich, UK. He has a PhD in Computational Modelling and an MBA in Technology Management and has published over 300 papers on the Design and Simulation of Electronics Packaging. Chris has served on several government committees, which includes the 2014 UK Research Excellence Framework, to assess research outputs and research impact across UK universities. He is a member of the EPSRC College (UK Equivalent to the NSF in the USA); and associate editor for the IEEE Transactions of Components, Packaging, and Manufacturing Technology. He is also the chair for the modelling and simulation technical working group on the Heterogeneous Integration Roadmap.
Xuejun Fan is a Regents’ Professor of Texas State University System, and a Mary Ann and Lawrence E. Faust Endowed Professor at Lamar University, Beaumont, Texas. He is an IEEE Fellow, and an IEEE Distinguished Lecturer. He currently serves as a member-at-large of the IEEE Electronic Packaging Society (EPS) Board of Governors. He gained significant experience in the microelectronics industry between 1997 and 2007, at IME, Philips and Intel. He received the Outstanding Sustained Technical Contribution Award in 2017, and Exceptional Technical Achievement Award in 2011, from the IEEE Electronic Packaging Society. He is also co-chair for the modelling and simulation technical working group on the Heterogeneous Integration Roadmap.
Upcoming Conferences
With the health and safety of our members and participants being our first priority, please know that our thoughts are with those affected by the COVID-19 outbreak.
We are closely monitoring the developments related to this pandemic and working diligently with the IEEE and our conference organizing committees worldwide, on our preparedness. Some of the conferences sponsored by our society that are scheduled to be held during these challenging few months have been already rescheduled or canceled. Others that are coming up in the later part of this year are carefully watching the developments and ready to make swift decisions, as needed.
This page will be updated on a weekly basis, as the situation keeps changing dynamically.
ECTC 2020 Virtual Event Open until July 7th
The 2020 ECTC Virtual Conference will be open until July 7, 2020. Registration is free!
You will have free access to more than 400 presentations featuring an outstanding array of packaging technology, including all aspects of advanced packaging: wafer-level and fanout packaging, 3D/TSV, interposers, assembly, materials, modeling, interconnections, reliability, wire bonding, and optoelectronic technologies. There is also a special session on the Heterogeneous Integration Roadmap. More details on how to directly access the HIR workshop can be found here.
ECTC CONFERENCE ENTRANCE PAGE: https://webinars.on24.com/
ACCESS TO MATERIALS: You must click the check box of each session that you would like to view
CONFERENCE OPENS: NOW OPEN!
CONFERENCE CLOSES: Tuesday, July 7, 2020 @ 5:00PM EDT
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