Heterogenous Integration for AI Chips
Authors: Yasumitsu Orii and Atsushi Takahashi
Introduction
The amount of compute used in the largest AI training runs has been increasing exponentially with a 3.4-month doubling time. It would be hard to sustain this growth if the AI chip development depends solely on the semiconductor process advancement since Moore’s Law has a 2-year doubling period and there is concern it is reaching its physical limit. The question this is how do we improve the computer hardware performance? The Von Neumann bottleneck is always the issue and Heterogenous Integration can provide good solution paths. And in recent years, chiplets, which allow us to achieve efficient high-performance computing better than ever before, have become the focus of the industry in response to the concern that Moore’s Law scaling is nearing its end. Another approach to resolve the Von Neumann bottleneck is to implement a neuromorphic device. We will discuss the key interconnection technologies such as high-density substrate, wafer level fan-out and Bridge to support chiplets and Neuromorphic devices.
Remembrances of Dr. Avram Bar-Cohen
Do you recall a personal interaction or anecdote about Avi Bar-Cohen? If so, we invite you to outline your story for a special section in this summer’s EPS NEWSLETTER, where a number of them will be published. Editing these recollections will be Paul Wesling; you can communicate directly with him (p.wesling@ieee.org), or outline your ideas here:
EPS Israel Chapter: AME - Printing A New Era of Electronics
IEEE EPS Israel in collaboration with the Chamber of Engineers invites you to the first online Israeli conference on 3D printing of electronics (Additive Manufacturing of Electronics). At the conference we will get acquainted with the basic concepts in the field of AME, we will get to know technologies, materials and some of the leading players in the field in Israel and around the world.
EPS University of Waterloo Webinars
Title: "3D System Integration"
Speaker: Dr. Jaber Derakhshandeh, IMEC
Date: March 31, 11:00 a.m. – 12:00 p.m. EDT
Title: Emerging 2.5D and 3D Heterogeneous Integration Architectures for the Next Phase of Moore’s Law
Speaker: Prof. Muhannad S. Bakir
Date: April 13, 3:00 p.m. – 4:00 p.m. EDT
Upcoming Webinars from the Silicon Valley EPS Chapter
We invite technologists from around the world to visit the SCV Chapter’s website (www.ieee.org/scveps) and sign up for the webinars that interest you:
Additively-Printed Multilayer Flexible Substrates with Z-axis Interconnects (Pradeep Lall) — aerosol-jet, inkjet, direct-write, screen print, multi-layer, process factors, performance …
March 18, 2021 at 12:00 pm PDT/3:00 pm EDT
Sustainable Electronics – From Dumped e-Waste to a Circular Economy: What is Needed?(Mervi Kröckel) — legislation, EU targets, recycling steps, applied ecodesign, carbon neutrality, case studies …
April 15, 2021 at 12:00 pm PDT/3:00 pm EDT
Packaging and Interconnect Technologies for Cryogenic and Quantum Systems(Michael Hamilton) — thin-film, multi-conductor, flexible, superconducting cables, low insertion loss …
April 22, 2021at 12:00 pm PDT/3:00 pm EDT
Results of Low-Temperature Polyimide Processing for Interconnect RDL in Next-Generation 3D Advanced IC Backend Applications(Zia Karim) — faster cure, lower temperatures, vacuum, thermal stability, properties …
May 6, 2021 at 12:00 pm PDT/3:00 pm EDT
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