ITHERM 2022
21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm 2022) 
Sponsored by IEEE EPS
Co-located with the 72nd ECTC 2022 – Joint registrations available at discounted rate
When: May 31 – June 3, 2022
Where: Sheraton Hotel & Marina San Diego, CA USA
ITherm 2022 is an international conference for scientific and engineering exploration of thermal, thermomechanical and emerging technology issues associated with electronic devices, packages and systems. In addition to paper presentations and vendor exhibits, ITherm 2022 will have keynote lectures by prominent speakers, panel discussions, invited Tech Talks, professional development courses and several student design competitions.
All papers will be peer reviewed and published in the ITherm proceedings on IEEE Xplore. Student first authors will have the opportunity to apply for ITherm travel grants in order to make an oral presentation and participate in a Student Poster and Networking Session.
Our abstract submission website is now open, and we encourage your submissions through the extended deadline of September 20, 2021. Review the details in our Call for Abstracts.
EPTC 2021 Call For Registration
ABOUT EPTC
The 23rd IEEE Electronics Packaging Technology Conference (EPTC2021) is an international event organized by the IEEE RS/EPS/EDS Singapore Chapter and co-sponsored by IEEE Electronics Packaging Society (EPS). It aims to provide a platform for the dissemination of innovations and new developments in semiconductor packaging and component technology, from design to manufacturing. Since its inauguration in 1997, EPTC has been established as a highly reputed electronics packaging conference and is the EPS flagship conference in the Asia-Pacific Region 10. It covers diverse areas of electronics packaging technology including modules, components, materials, equipment technology, assembly, reliability, interconnect design, device and systems packaging, heterogeneous integration, wafer-level packaging, flexible electronics, LED, IoT, 5G, autonomous vehicles, photonics, emerging technologies, 2.5D/3D integration, and smart manufacturing. EPTC2021 features keynotes, technology talks, invited presentations, technical presentations, sponsorship & exhibition corners, and virtual networking activities.
Top T-CPMT Papers on Xplore
You can find the most accessed T-CPMT articles on Xplore here
Co-design and Co-analysis of 3D Integrated Electronics
Rohit Sharma1, Jose E. Schutt-Aine2, Wiren Dale Becker3
1 Department of Electrical Engineering, Indian Institute of Technology Ropar, Rupnagar, INDIA
2 Department of Electrical and Computer Engineering. University of Illinois Urbana-Champaign Urbana, IL 61801, USA
3 IBM, Poughkeepsie, NY, USA
rohit@iitrpr.ac.in; jesa@illinois.edu; wbecker@us.ibm.com
Abstract
In this paper, we present an overview of the electrical-thermal co-design and co-analysis of 3D ICs in heterogeneously integrated systems. We present the generalized framework for electrical-thermal co-design. The application of electrical-thermal co-design and co-analysis as applied to chiplets is addressed.
Upcoming Emerging Technologies TC Webinar
Title: Ultrafast Time Domain Cryogenic CMOS Device Characterization Platform for Quantum Computing Applications
Date: September 30, 2021
Time: 12:00 pm PDT/3:00 pm EDT
Presenter: Pragya Shrestha, NIST
You can earn 1 Professional Development Hour (PDH) for attending this webinar by completing the PDH survey form
Abstract: Cryogenic electronics have a wide range of applications, ranging from quantum information science to extra-terrestrial electronics to gravitational wave research to high performance computing. However, the dominant application leading the way for cryogenic electronics research, is quantum computing where electronic functionality at the 4 K or below has become a requirement. The most promising candidate to fulfil this functionality without disturbing the cryogenic environment with a path to large-scale integration is CMOS. Therefore, a lot of effort has been put in to hunt for the right CMOS device technology and obtain their low temperature models for designing reliable and accurate cryogenic circuits. Though it has been acknowledged that precise characterization is crucial for reliable low power and low temperature circuit design, obtaining reliable device characterization and reliability at low temperatures has not been sufficiently addressed. Absent specially is the time domain characterization of devices which are crucial for designing accurate analog circuitry. This webinar will review the challenges of using cryogenic CMOS in the field of quantum computing and further discuss the motivation for creating cryogenic ultra-fast time domain device characterization setup for accurate high-performance cryogenic CMOS circuit design.