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The Electronic Components and Technology Conference (ECTC) is the premier international event that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange. ECTC is sponsored by the IEEE Electronics Packaging Society.

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Technical Program

Professional Development Courses

The Silicon Valley EPS chapter invites engineers around the world to their free virtual technical seminars scheduled for 2021.  For an updated full listing, visit http://www.ieee.org/scveps.  Links to past events held so far this year (e.g., HIR Symposium, Technical Working Group meetings, and follow-up discussion sessions) can also be found on the Chapter’s website.

Luu Nguyen, Director of Programs,EPS Silicon Valley Area Chapter

April 22, 2021 – Noon Pacific:  Packaging and interconnect technologies for cryogenic and quantum systems,” M. Hamilton, Auburn University.

May 6, 2021 – Noon Pacific:  Results of low-temperature polyimide processing for interconnect RDL in next generation 3D advanced IC backend applications,” Z. Karim, Yield Engineering Systems.

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Title: Wafer-Scale Heterogeneous Integration

Date: April 22, 2021

Time: 11:00 AM – 12:00 PM

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Abstract: Silicon interconnect fabric (Si-IF) promotes a paradigm shift in ultra-large-scale heterogeneous integration. The Si-IF is a wafer-scale platform that supports integration of heterogeneous bare (unpackaged) dies. The dies are connected using fine pitch vertical interconnects (pillars) designed directly on the Si-IF, effectively eliminating the need for package and printed circuit board. The pitch of the vertical pillars that are used to bond dies to the Si-IF is 2 to 10 μm, and the minimal distance between adjacent dies on the Si-IF is approximately 50 μm. The Si-IF supports SoC-like integration at a wafer level, enabling scaled out applications that were previously not practical (e.g., neuromorphic systems).

To enable the Si-IF as a practical platform for ultra-large-scale heterogeneous integration, system-level design challenges must be addressed. Borrowing from a network-on-chip (NoC), a network on interconnect fabric (NoIF) is proposed to support global communication on the Si-IF. Unlike NoCs, the NoIF is expected to provide additional system-level services, including power management, synchronization, and testing (built-in self-test) on the Si-IF. The Si-IF is a passive platform; utility dies (UDs) serve, therefore, as intelligent nodes within the NoIF to support all of the services that the network provides.

Title: Avoiding inelastic strains in solder joint interconnections of IC packages

Presenter: Dr. Ephraim Suhir, Portland State University, Portland, OR, USA    

Date: Thursday, April 22, 2021 

Time: 5:00 - 6:30 PM (PDT) 

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Abstract: The following three practically important questions associated with predicting and improving the reliability of solder joint interconnections (SJI) of IC packages are addressed in this seminar: (a) Could inelastic strains in the solder material be avoided by a rational design, and if not, could the sizes of the inelastic strain areas be predicted and , if possible, minimized? (b) Considering that the difference between an highly reliable and an insufficiently reliable product is “merely” in the level of its never-zero probability of failure, and that SJIs are usually the most vulnerable structural elements in an IC package design, could this probability be assessed at the design stage and, if possible, made adequate for the given application? (c) Should temperature cycling accelerated testing for SJIs be replaced with a more physically meaningful, less costly, less time- and labor- consuming and, most importantly, less misleading accelerated test vehicle? Dr. Suhir will cover these topics from his book linked here. IEEE EPS/EDS Pittsburgh Webinar: Avoiding inelastic strains in solder joint interconnections of IC packages.

Title: Trends in Thermal Management of Electronic Systems

Date: 09 Jun 2021

Time: 04:30 PM to 05:45 PM (All times are Europe/Zurich)

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Abstract: This webinar will include a talk on roadmap of thermal management in heterogenous integration and two talks on trends in advancing  thermal management for high power devices.


16:30 - 16:35 : Welcome and Introduction

16:35 - 17:10 : "Heterogeneous Integration Roadmap Thermal Technical Working Group (TWG) Update", Dr. Weihua Tang, Intel Corporation, USA

17:10 - 17:25 : "Passive two-phase cooling in power electronics", Dr. Daniele Torresin, Principal Scientist, ABB Research Center, Switzerland

17:25 - 17:40 : "Active cooling: a solution for low TCE, high thermal conductivity packages", Dr. Arno Hoogerwerf, Senior Expert, CSEM SA, Switzerland

17:40 - 17:45 : General discussions and closure 


The video conferencing link will be provided to registered attendees.

EPS is pleased to announce the revitalization of the IEEE EPS Orange County Chapter.

More information on upcoming chapter webinars and events will be provided in future e-newsletters.

Abstract: Future implantable biomedical systems will require power and data telemetry with multiferroic interfaces, signal modulation, low-impedance electrodes with high current injection, remateable connectors  - all in a highly miniaturized form-factor with reliability in a reactive aqueous environment. They provide a combination of functions such as neural recording and stimulation, imaging, spectroscopy, electrochemical sensing and others. They, thus, drive the most advanced heterogeneous integration. Advancing system components and their 3D connectivity in small form-factors are both critical to realize such future medical implants. The system components are advanced through innovative nanomaterials, multiphysics-based material designs to achieve the performance metrics, and hybrid additive and semi-additive manufacturing technologies. The integration technologies rely on advanced chiplet fan-out embedding technologies in flexible or rigid-flex substrates that provide seamless but reliable interconnect technologies between the system components. This article will briefly review some of the key functional packaging build blocks towards these heterogeneous 3D implanted medical systems.

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IMPACT 2021 Conference, organized by IEEE-EPS-Taipei, iMAPS- Taiwan, ITRI and TPCA, is the largest gathering of PCB and packaging professionals in Taiwan. This year will be held on Oct. 20th - 22nd at Taipei Nangang Exhibition Center, in conjunction with TPCA Show 2021. For grasping the latest trend, the symposium this year highlights the theme “IMPACT on 5G+”. As the rapid growth of 5G coverage over the world, the 5G commercial network enables an array of revolutionary technologies such as loT, artificial intelligence (AI), edge computing and wearable devices. Given the foundational infrastructure is advancing along with technologies, 5G brings faster speed and connectivity to those using it.

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Date: November 10 – 12, 2021,

A Hybrid Event of On-site and Virtual Meetings

On-site Venue: Kyoto University Clock Tower Centennial Hall, Kyoto, JAPAN


“Electronics Packaging for 5G and B5G”

“IEEE CPMT Symposium Japan (ICSJ)” is one of the most widely recognized international conferences sponsored by the IEEE Electronics Packaging Society (EPS) and has been held annually in Kyoto in November. This conference was inaugurated in 1992 as “The VLSI Packaging Workshop in Japan (VPWJ)” to provide a platform for you to communicate and interact with global leaders in packaging technology. Later in 2010, this conference was renamed to “ICSJ” and ICSJ2021 is the 10th ICSJ meeting, or 19th conference since establishing VPWJ. This year, ICSJ2021 will be a hybrid event of on-site and virtual meetings where several presentation options are available for the authors to select and the details will be announced on the official website at a later date.

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You can find the most accessed T-CPMT articles on Xplore here