Title: Wafer-Scale Heterogeneous Integration
Date: April 22, 2021
Time: 11:00 AM – 12:00 PM
Abstract: Silicon interconnect fabric (Si-IF) promotes a paradigm shift in ultra-large-scale heterogeneous integration. The Si-IF is a wafer-scale platform that supports integration of heterogeneous bare (unpackaged) dies. The dies are connected using fine pitch vertical interconnects (pillars) designed directly on the Si-IF, effectively eliminating the need for package and printed circuit board. The pitch of the vertical pillars that are used to bond dies to the Si-IF is 2 to 10 μm, and the minimal distance between adjacent dies on the Si-IF is approximately 50 μm. The Si-IF supports SoC-like integration at a wafer level, enabling scaled out applications that were previously not practical (e.g., neuromorphic systems).
To enable the Si-IF as a practical platform for ultra-large-scale heterogeneous integration, system-level design challenges must be addressed. Borrowing from a network-on-chip (NoC), a network on interconnect fabric (NoIF) is proposed to support global communication on the Si-IF. Unlike NoCs, the NoIF is expected to provide additional system-level services, including power management, synchronization, and testing (built-in self-test) on the Si-IF. The Si-IF is a passive platform; utility dies (UDs) serve, therefore, as intelligent nodes within the NoIF to support all of the services that the network provides.