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The EPS President Elect review process is underway. To qualify for nomination, the candidate for President-Elect (and subsequently President) shall have been at some time an elected Member-at-Large or Vice President (Per EPS Bylaws).  The deadline for nominations is Friday 17th July. The final vote will take place during the Fall Board of Governors Meeting.

Nomination Form.

For a limited time, the Best Papers from ECTC 2021 will be available as Open Access

1)      Best Session Paper
  Proof of Concept: Glass-Membrane Based Differential Pressure Sensor
Anatoly Glukhovskoy - Leibniz University, Maren S. Prediger - Leibniz University, Jennifer Schäfer- Leibniz University, Norbert Ambrosius - LPKF Laser & Electronics AG, Aaron Vogt - LPKF Laser & Electronics AG, Rafael Santos - LPKF Laser & Electronics AG, Roman Ostholt - LPKF Laser & Electronics AG, and Marc Christopher Wurz - Leibniz University

2)      Best Interactive Presentation Paper 
  System in package embedding III-V chips by fan-out wafer-level packaging for RF applications
Arnaud Garnier, Laetitia Castagné, Florent Gréco, Thomas Guillemet, Laurent Maréchal, Mehdy Neffati, Rémi Franiatte, Perceval Coudrain, Stéphane Piotrowicz, and Gilles Simon - CEA-Leti. Authors 1-3, 7, 8, 10: CEA-Leti, Author 4: Thales DMS, Authros 5, 6: United Monolithic
Arnaud Garnier - CEA-Leti, Laetitia Castagné - CEA-Leti, Florent Gréco - CEA-Leti, Thomas Guillemet - Thales DMS, Laurent Maréchal - United Monolithic Semiconductors, Mehdy Neffati - United Monolithic Semiconductors, Rémi Franiatte - CEA-Leti, Perceval Coudrain - CEA-Leti, Stéphane Piotrowicz - III-V Lab, Gilles Simon - CEA-Leti

3)      Outstanding Session Paper
 Ultra-Thinning of 20 nm-Node DRAMs down to 3 um for Wafer-on-Wafer (WOW) Applications
Zhiwen Chen - Tokyo Institute of Technology, Naoko Araki - Tokyo Institute of Technology, Youngsuk Kim - Tokyo Institute of Technology, Tadashi Fukuda - Tokyo Institute of Technology, Koji Sakui - Tokyo Institute of Technology, Tomoji Nakamura - Tokyo Institute of Technology, Tatsuji Kobayashi - Micron Memory Japan, Takashi Obara - Micron Memory Japan, and Takayuki Ohba - Tokyo Institute of Technology 

4)      Outstanding Interactive Presentation Paper 
  Cu Recrystallization and the Formation of Epitaxial and Non-Epitaxial Cu/Cu/Cu Interfaces in Stacked Blind Micro Via Structures
T. Bernhard, S. Dieter, R. Massey, S. Kempa, E. Steinhäuser, F. Brüning. All authors: Atotech Deutschland GmbH.

5)      Intel Best Student Session Paper
  Mechanical Behavior and Reliability of SAC+Bi Lead Free Solders with Various Levels of Bismuth
KM Rafidh Hassan, Jing Wu, Mohammad S. Alam, Jeffrey Suhling, and Pradeep Lall. All authors: Auburn University

The EPS Technical Committee meetings to be held during ECTC 2022 are as scheduled.

Attendance is open to all.

 Technical Committee                  Date                    Time                                 Room

EPS Power & Energy TC            6/1/2022            7:00 am – 8:00 am           514

EDMS TC                                    6/1/2022            7:00 am – 8:00am            Driftwood 1

Reliability TC                               6/1/2022            7:00 am – 8:00am            Driftwood 2 

Emerging Tech TC                      6/2/2022            7:00 am – 8:00am            Driftwood 1

Photonics TC                              6/2/2022            7:00 am – 8:00am            Driftwood 2

Nanotechnology TC                    6/2/2022            7:00 am - 8:00 am           511

EPS RF & Thz Techn. TC/

ECTC Components Committee          6/3/2022             7:00 am – 8:00am           514 

3D TSV TC                                 6/3/2022             7:00 am – 8:00am           Driftwood 2


A Heterogeneous Integration Roadmap (HIR) Workshop will be held in conjunction with ECTC and ITherm this year.

Location:  The Sheraton San Diego Hotel and Marina

Date: May 31, 2022

Time: 8:00 am - 5:00 pm

In Person Only


The 24th IEEE Electronics Packaging Technology Conference (EPTC2022) will be held December 7th -9th, 2022 in Singapore. Authors are invited to submit  abstracts between 500–750 words long and clearly state the purpose, methodology, results (which must include data, drawings, graphs and photographs) and conclusions of the work.  Additional details on abstracts submission can be found on the EPTC website. Abstracts must be received by June 30, 2022.

For more details

Title: Solder joints interconnections in automotive electronics: could low cycle fatigue conditions in them be avoided

Date: Thursday, Apr 21, 2022 

Time: 3pm – 4pm (EDT)

Presenter: Ephraim Suhir

Abstract: Three practically important problems associated with the reliability of solder joint interconnections (SJI) in IC packages are addressed:

1) Could inelastic strains in the solder material be avoided by a rational physical design, and if not, could the sizes of the inelastic strain areas be predicted and minimized? SJIs are the most vulnerable structural elements in the today’s IC packages: the solder material often experiences inelastic strains, and, because of that, suffers from low cycle fatigue conditions, and its fatigue lifetime is often shorter than required for many applications. There is an obvious incentive therefore to explore ways to bring down the induced stresses and strains in this material, even, if possible, to an extent that the inelastic strains are avoided. If this is impossible, the size of the inelastic zones could be, desirably, predicted and minimized.

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 Join Webinar here

Title: Advanced Packaging in Hyperscale Data Center Applications

Date:  May 6, 2022

Time:  12:00 pm EDT

Platform:  Webex

Presenter: Jie Xue, Vice President Technology & Quality, Cisco Systems, Inc.

Register here


Advanced Packaging technologies including Silicon and Silicon photonics are key enablers for scaling Hyperscale Data Center. This talk will discuss the roadmap of technology building blocks with a focus on increasing in performance while reducing power per Gbps. Challenges toward device integration, reliability and industry eco-system collaboration will also be elaborated.

BioJie Xue leads Cisco’s Technology and Quality organization, a global team responsible for pathfinding, developing, and executing technology innovations to enable all Cisco networking product portolio. Jie oversees development of leading edge technologies for Si-Photonics, Advanced Si, ASICs, PCBs, Optics, memory, and complex interconnect technologies.

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IEEE EPS Malaysia AGM - 12th February, 2022

This year IEEE EPS Malaysia Chapter held their AGM 100% Online.  Please join me in congratulating the incoming IEEE Electronic Packaging Society (EPS) Malaysia Chapter committee that is led by Dr Yik Yee TAN.

IEEE Malaysia Chapter Won the IEEE Malaysia Section - 2021 Outstanding Small Chapter Award

During the 2022 IEEE Malaysia Section AGM held at Kuala Lumpur Convention Centre on 12th Feb 2022, IEEE EPS Malaysia Chapter, chaired by Dr Yik Yee Tan won the 2021 Outstanding Small Chapter Award.   The purpose of the award is to recognize the outstanding performance of the small chapter among all the small chapters in Malaysia Section. 

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Benson Chan, Mark Hoffmeyer, Eugene M. Chow, Ivy Qin, Daehan Won, SB Park

Abstract—This paper details several current examples of Industry 4.0 [10] activity involving application of emerging technologies used for the Smart Manufacture of computer systems and affiliated electronics. Highlights include Smart Manufacturing methods in development and in current production, where the use of artificial intelligence and machine learning is leveraged to improve quality, yield, and reliability at a reduced overall manufacturing cost.

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Wendemagegnehu T. Beyene, Senior Member, IEEE

Chiplets and heterogeneous integration are changing the design of modern electronic systems. Instead of only relying on process shrinks as the primary driver of product design and system performance, the heterogenous multi-chiplet architectures can potentially provide a much lower cost alternative to the latest design nodes. Packaging technology is poised to play a key role in the performance of the next generation systems. The chiplet-based design can be built on various materials such as silicon, glass, and organic laminate. The resulting single-package-based integration allows multiple silicon dies of various technology and complexity to be integrated efficiently using next-level interconnects, such as silicon interposers and bridges.

As the systems evolve from single monolithic devices to multi-chiplet architectures, the electrical analysis become more critical to guarantee the performance of such heterogenous systems. The second-level interconnects provide a low-impedance power delivery path between multiple independent power domains and short inter-die interconnects. The physical layer can either be parallel or serial interface trading power, latency and area or beachfront. Since these interconnects are short, the signal integrity may not initially pose a challenge. However, elevated transient currents of multiple dies and their unique clocking architecture make the supply noise, jitter, and latency the limiting factors in designing high-performance multi-die heterogenous systems. In this paper, chiplet packaging technology as well as the design and analysis of the heterogeneous systems are reviewed. 

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