Wendemagegnehu T. Beyene, Senior Member, IEEE
Chiplets and heterogeneous integration are changing the design of modern electronic systems. Instead of only relying on process shrinks as the primary driver of product design and system performance, the heterogenous multi-chiplet architectures can potentially provide a much lower cost alternative to the latest design nodes. Packaging technology is poised to play a key role in the performance of the next generation systems. The chiplet-based design can be built on various materials such as silicon, glass, and organic laminate. The resulting single-package-based integration allows multiple silicon dies of various technology and complexity to be integrated efficiently using next-level interconnects, such as silicon interposers and bridges.
As the systems evolve from single monolithic devices to multi-chiplet architectures, the electrical analysis become more critical to guarantee the performance of such heterogenous systems. The second-level interconnects provide a low-impedance power delivery path between multiple independent power domains and short inter-die interconnects. The physical layer can either be parallel or serial interface trading power, latency and area or beachfront. Since these interconnects are short, the signal integrity may not initially pose a challenge. However, elevated transient currents of multiple dies and their unique clocking architecture make the supply noise, jitter, and latency the limiting factors in designing high-performance multi-die heterogenous systems. In this paper, chiplet packaging technology as well as the design and analysis of the heterogeneous systems are reviewed.