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The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members at Large will be selected each year to represent the regional composition of the Society membership and one Member at Large will be selected to represent the Young Professional community . A Young Professional is an individual that has completed their first academic degree within the last 15 years.

 Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG.  The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect members-at-large from within their Region only (that is, members in Region 8 vote for Members-at-Large from Region 8, members in Region 10 vote for Members-at-Large from Region 10; etc.)

The Young Professional Member at Large will be elected by all members of the Society from a slate that is finalized by the Nominations Committee

Date: Tuesday, May 30, 2023

Time: 8:00 am – 4:30 pm (Eastern Time)

Location: JW Marriott Orlando Grande Lakes, Orlando FL

Special Sessions

-AI/ML in Package Co-Design for Chiplets Perspective

-Heterogeneous Integration of MEMS & Sensors : Challenges and Opportunities

-The CHIPS and Science Act

-Additively Manufactured Electronics for Heterogeneous Integration

Register here for ECTC or ITherm (HIR Workshop included with registration)

12th IEEE CPMT Symposium Japan (ICSJ2023)

“Advanced Packaging for Chiplet Era”

15 -17 November, 2023 

Ritsumeikan University Suzaku Campus, Kyoto, JAPAN


Abstract deadline 29 May, 2023

“IEEE CPMT Symposium Japan (ICSJ)” is one of the most widely recognized international conferences sponsored by the IEEE Electronics Packaging Society (EPS) and has been held annually in Kyoto in November. The past two years of ICSJ events were a hybrid meeting with virtual and on-site event, but this year, ICSJ2023 will be only on-site meetings since the pandemic settles down.

Advanced Packaging for Chiplet Era: Chiplet architecture, moving from monolithic to multi-tile devices, is becoming a key technology to expand computing resources with integrated functional units on a same package. Chiplet is not only driving the packaging technology including 2.xD/3D integration and high density substrate technology with process and material, but also revolutionizing applications requiring highly advanced computing such as 5G, AI, automotive, edge computing and mobile components. The symposium tries to forecast where the packaging technology is heading. In 2023, our focus is on key electronics packaging technologies pulling by Chiplet architecture on the following main topics: Photonics, Advanced Packaging, Process & Material, Power & Automotive Electronics, Bioelectronics & Healthcare, and Signal/Power Integrity.

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 23 -  24 May, 2023

 Georgia Institute of Technology, Atlanta, Georgia

The Glass Packaging Workshop 2023 (GPW2023), co-sponsored by IEEE brings together sponsors, designers, developers, users, and supply-chain manufacturers to share the latest advances in glass packaging.

Glass panel packaging promises to add a variety of strategic needs: a) In HPC for higher performance, lower costs, and improved reliability; b) In automotive for improved high-temperature reliability; c) In wireless for 6G integrated antennas; d) In consumer electronics for ultra-miniaturization and lower cost.  To enable all these, a global manufacturing ecosystem needs to be set up from R&D to manufacturing to enable the above products and applications.

Registration info

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Title: Sustainable Smart Lighting Technology State-of-Art and Roadmap to the Future

Date: 28 July, 2023

Time: 11:00 AM - 12:00 PM (UTC-04:00) Eastern Time (US & Canada)

Presenter:  Prof. Georges Zissis, PhD, SMIEE

Register here


During the last decade, SSLs-Solid-State Lighting based on components like LEDs, OLEDs, and LDs, challenges conventional technologies. LED has turned into a game changer beating conventional technologies in all aspects. It is therefore anticipated that in short term, all the electric lighting will be based on SSLs. Today, SSLs proceed to the projected conclusion: replacing all legacy technologies, this is a major change in the lighting market that is considered a revolution. 

Artificial light production absorbs around 2 900 TWh corresponding to 16.5% of the world’s electricity annual production. Historically speaking, the past century’s research and development focused on single-energy efficacy enhancement. During the last decade, Solid-State Lighting (SSL) based on components like LEDs, OLEDs, and LDs, challenges conventional technologies. LED has turned into a game changer beating conventional technologies in all aspects. It is therefore anticipated that in short term, all the electric lighting will be based on SSLs. That way, SSLs proceed to the projected conclusion: replacing all legacy technologies, this is a major change in the lighting market that is considered a revolution. 


Prof. Georges ZISSIS, PhD, SMIEE, Vice-Rector Toulouse 3 University (2020-23). Born in Athens in 1964, has graduated in 1986 from Physics department of University of Crete in general physics. He got his MSc and PhD in Plasma Science in 1987 and 1990 from Toulouse 3 University (France). He is today full Professor in Toulouse 3 University (France). His primary area of work is in the field of Light Systems Science and Technology. 

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 Call for Abstracts – Fourth Annual REPP (Please submit by August 15)

Symposium on Reliability for Electronics and Photonics Packaging

Reliability, Failure Modes and Testing for Integration of Electronics and Photonics (SiPh)

REPP’23 is planned to be a hybrid event, with both in‐person and WebEx participation This symposium will focus on quantified reliability, accelerated testing and probabilistic assessments of the useful lifetime of electronic, photonic, MEMS and MOEMS materials, assemblies, packages and systems in electronics and photonics packaging. This includes failure modes, mechanisms, testing schemes, accelerated testing, stress levels, and environmental stresses.

The intent is to bring together electrical, reliability, materials, mechanical, and computer engineers and applied scientists to address the state‐of‐the‐art in all the interconnected fields of electronic and photonic packaging, with an emphasis on various reliability‐related aspects: design‐for‐reliability, manufacturing, reliability modeling and accelerated testing.

Proposals for presentations in the fields of Reliability for Electronic and Photonic Packaging are solicited, for either in‐person or remote presentation.

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Abram Detofsky, IEEE Member and Intel Principal Engineer

Intel Corporation, 2200 Mission College Blvd, Santa Clara CA 95054; abram.m.detofsky@intel.com

Abstract—The number and variety of chiplet-based designs is expected to flourish in the coming years, driven by manufacturing optimization, R&D costs, product velocity and Design flexibility needs, amongst others. This article describes the architectural Design and Test challenges and proposed strategies to enable resilient products in a chiplet-based world. Keywords— Semiconductor, Multi-die Packages, Heterogeneous Integration (HI), Test, Functional Test, Structural Test, System Level Test (SLT), Production Test Flow. I. INTRODUCTION The relentless evolution of performance-hungry and diverse customer workloads can be addressed by innovations in silicon scaling, algorithm, software, and architectural changes and through advanced packaging [1]. Fig. 1 shows a number of major innovation vectors that need to be pursued for continued compute performance scaling. Historically, the emphasis has been primarily on the silicon and software-based vectors. In recent years there has been a renaissance of advanced packaging innovation to meet the needs of new customer workloads. Gordon Moore predicted this day back in 1965 when he stated, “It may prove to be more economical to build large systems out of smaller functions which are separately packaged and interconnected.” [2]

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Daniel Donahoe

Past Chair IEEE Utah Section and Milestone Proposer 

I learned that I had been elected to serve as Chair of the IEEE Utah Section 2020-2021 on November 10, 2019. As I had served on the IEEE-USA Board 2016-2017 and completed a statistical membership review of US members, I had insight into membership challenges. Preparing to assume this section office, I found that the section’s chapter of the largest of IEEE’s technical societies had gone inactive (i.e., “sunk”), the Computer Society. As the Utah business community considers computing its strong point, I struggled with leadership ploys that might raise this sunken (computer) ship. Luckily, I attended the Region 6 OpCom in Los Angeles in early February of 2020. I knew Brian Berg from the Santa Clara Section when I served in SCV/EPS chapter roles up to chair in 2007, and I knew Brian had been deeply immersed in several meaningful IEEE Milestones. I proposed a Utah Milestone for early computer graphics work in Utah, and Brian vigorously agreed. But I had no idea of the arduous process laying in wait. I should have known, because I do recall SCV’s Dick Ahrons once so commenting at a section meeting.

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You can find the most accessed T-CPMT articles on Xplore here

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