The EPS Board of Governors voted unanimously to establish a PhD Fellowship award in the area of electronics packaging. Graduate Students - Here is what you need to know:
To promote, recognize, and support PhD level study and research within the Electronics Packaging Society’s field of interest.
A plaque and a single annual award of US$5,000, applicable towards the student’s research.
Candidate must be an IEEE EPS member, at the time of nomination, and be pursuing a doctorate degree within the EPS field
of interest on a full-time basis from an accredited graduate school or institution.
The candidate must have studied with her/his advisor for at least 1 year, at the time of nomination, to be eligible.
A Student who received a Fellowship award from another IEEE Society, within the same year, or is a previous EPS Fellowship
winner is ineligible.
Nomination Period to Open September 15
Please refer to the EPS website for additional details
The voting period for EPS Members At Large will open September 4, 2018. All voting members of the Society will receive a notification.
The IEEE Electronics Packaging Society Constitution and Bylaws provide that each year the membership shall elect six Members-at-Large to the Society Board of Governors to serve a three-year term. Members-at-large will be elected to achieve totals proportionate to the geographic distribution of EPS members. For 2018, this translates as follows:
- Regions 1-6, 7 and 9 (US, Canada, South and Central America): elect 3 members
- Region 8 (Europe, Africa, Middle East): elect 0 member
- Region 10 (Asia/Pacific): elect 3 members
The six newly elected Members-at-Large will join continuing Members-at-Large (shown below) on the Board of Governors:
Regions 1-6,7,9: Li Li, David McCann, Kitty Pearsall, Subramanian S. Iyer
Region 8: Thomas Brunschwiler, Gilles Poupon
Regions 1-6, 7,9 -- Alan Huffman, Sam Karikalan, Xuejun Fan, Jeffrey C. Suhling;
Region 8 -- Grace O'Malley; Region 10 -- Yoichi Taira
Voting members will elect Members-at-Large from within their respective Regions only, that is, members in Region 10 will vote for Members-at-Large from Region 10 only, etc.
To promote student participation at the ECTC, EPS has travel to ECTC for 8 students.
A certificate and reimbursable travel expenses up to the limits of $1,300 US for students at US institutions and $2,100 US for students at non-US institutions.
Twenty candidates are preliminary selected based on the ECTC technical committee scoring and a balance among the various committees. The student paper must be accepted to be presented at the conference, and the student must be the presenter and the paper first author. The candidates are requested to submit an extended abstract. A committed of up to 5 evaluators then rate the extended abstracts and the top 8 are selected for the travel award.
New promotion to Latin American Students
An expansion of the ECTC student travel award program in support 2 graduate-level students from under-represented geographies at the ECTC was approved by the Board of Governors. Up to 2 students with accepted ECTC papers from Latino-America, Region 9, will be given travel a award. This is the first step in promoting EPS growth in Latino-America.
The Heterogeneous Integration Roadmap (HIR) held another successful workshop at SEMICON West. There was representation from Europe, Asia and the US. Twenty three participants attended the July 8th meeting and twenty nine attended the July 9th meeting held at the Moscone Center in San Francisco. Ajit Manocha, SEMI President & CEO and member of the HIR Global Advisory Council, opened the Monday session. Hubert Lakner, HIR Global Advisory Council member, also attended SEMICON West.
Upcoming HIR WorkshopsThursday, August 30, 2018
Hilton San Francisco
San Francisco, CA
Tuesday, September 18, 2018
Wednesday, Septenmber 19, 2018
Additional HIR workshops will be held throughout the remainder of the year. Please refer to the EPS website
ESTC 2018 has several Special Workshops scheduled for Wednesday afternoon, September 19th.
Hot topics in the field of electronic packaging are presented and discussed. Share your experiences and opinions with colleagues.
Access to those Special Workshops is included in the conference fee.
We look forward to seeing you at the conference.
Dr. Rodney Martens
If you wish to receive future communications regarding the upcoming conference, please send an email to .
The 2019 IEEE 69th Electronic Components and Technology Conference
The premier international packaging, components, and
microelectronics systems technology conference
You are invited to submit an abstract and/or a Professional Development Course (PDC) proposal about new developments and technology related to the following:
· Applied Reliability
· Assembly and Manufacturing Technology
· Emerging Technologies
· High Speed, Wireless and Components
· Materials & Processing
· Thermal/Mechanical Simulation and Characterization
· Packaging Technologies
· Interactive Presentations
Materials Impurities and Logic/Memory Errors: Join us on 24 October for the worldwide 10th EPS Soft Error Rate Workshop (no cost: in person or via full-day webinar). As packaging is developed for denser ICs and 2.5 and 3D, minor radioactive impurities can have a larger effect on system integrity. Presenters from IBM, Xilinx, Los Alamos Nat’l Lab, HPE, Stanford, Vanderbilt, SpaceX, Cypress Semi, Nvidia, STMicro and others will discuss issues, metrology, and use cases. Download past slides and view past presentations of interest.
For more information and to register:http://www.cpmt.org/scv/?p=679