Dear InterPACK Community,
The prestigious InterPACK Achievement Award has been renamed as the Avram Bar-Cohen Memorial Award in his memory, starting this year, 2021. Traditionally, InterPACK Achievement Award has been given to a single individual at each Conference. The same format will be followed for the Avram Bar-Cohen Memorial Award, with the winner to be announced prior to
the InterPACK 2021 Conference, to be held during October, 26 - 28, 2021.
Our 32nd Electronics Packaging Symposium will be held virtually this year.
This is a virtual symposium with live presentations. It will be held on September 8th at 10:00AM - 5:00PM, and September 9th at 10:00AM - 4:30PM.
Title: High Thermal Conductivity Materials Towards Efficient Thermal Management of Electronic Devices: Application And Modelling
Date: Sept. 30, 2021
Time: 16:00 [CET]
Presenters: Dr. Erich Neubauer, Managing Director, RPH Technology GMBH, Austria
Michiel de Monchy, Applications Manager Die Attach and Preforms Europe, Macdermid Alpha Assembly Solutions, The Netherlands
Guido Spinola Durante, Expert, CSEM SA, Switzerland
Abstract: As miniaturization trend for semiconductor chips continues, power density is increasing rapidly. So it has become very important, especially for high power semiconductors or high power lasers to remove the heat away from the chip efficiently and rapidly, to ensure a long life time for the chips. This webinar will focus on usage of high thermal conductivity materials as die attach and substrate materials for efficient heat removal.
Title: Ultrafast Time Domain Cryogenic CMOS Device Characterization Platform for Quantum Computing Applications
Date: September 30, 2021
Time: 12:00 pm PDT/3:00 pm EDT
Presenter: Pragya Shrestha, NIST
You can earn 1 Professional Development Hour (PDH) for attending this webinar by completing the PDH survey form
Abstract: Cryogenic electronics have a wide range of applications, ranging from quantum information science to extra-terrestrial electronics to gravitational wave research to high performance computing. However, the dominant application leading the way for cryogenic electronics research, is quantum computing where electronic functionality at the 4 K or below has become a requirement. The most promising candidate to fulfil this functionality without disturbing the cryogenic environment with a path to large-scale integration is CMOS. Therefore, a lot of effort has been put in to hunt for the right CMOS device technology and obtain their low temperature models for designing reliable and accurate cryogenic circuits. Though it has been acknowledged that precise characterization is crucial for reliable low power and low temperature circuit design, obtaining reliable device characterization and reliability at low temperatures has not been sufficiently addressed. Absent specially is the time domain characterization of devices which are crucial for designing accurate analog circuitry. This webinar will review the challenges of using cryogenic CMOS in the field of quantum computing and further discuss the motivation for creating cryogenic ultra-fast time domain device characterization setup for accurate high-performance cryogenic CMOS circuit design.
Sreejit Chakravarty, IEEE Fellow
Principal Engineer, Intel Corporation
Introduction. The increasing trend to integrate and package multiple dice into one SoC has been driven by yield, i.e. cost, considerations, need to integrate proprietary functionality from different sources into the SoC, etc. Semiconductor manufacturers responded by developing innovative interconnect and packaging technologies, including 2.5D and 3D variants. In 2.5D, dice are placed next to each other on a substrate and interconnected using special IOs.
The introduction of mmWave 5G introduces new challenges to interconnects and packaging. The higher frequencies means that interconnects between chips and board need to be low loss and high bandwidth. The additive manufacturing method enables a high level of integration between antenna and electronics and serves as the primary design tool to create low-cost and highly customizable wireless system designs which can enable rapid deployment of large-scale 5G communication and IoT systems. The versatility of additive manufacturing for packaging allows for customizable packaging structures and modules and allows designers to enable high performance with minimal tooling required. Additionally additive manufactured interconnects can enable novel structures which operate much better at higher frequencies than traditional methods. The nature of additive manufacturing allows electronics to be manufactured with very little waste and allows quick iteration allowing a drastic reduction in time-to-market. This article will discuss several packaging structures for mm-Wave capable modules utilizing additive manufacturing for use in communication, energy harvesting and reconfigurable surfaces.
M. Jensen, Intel Corporation
Semiconductor test is an exciting field and has over the past decades become increasingly challenging – requiring test engineers of all disciplines to push their limits in search of better, faster, and cheaper solutions.
Most packaged semiconductor products go thru a test flow that include elements of a burn-in process, a pattern-based structural test process, and - finally - a system level test process
November 10-12, 2021
A Hybrid Event of On-site and Virtual Meetings
On-site Venue: Kyoto Univ. Clock Tower Centennial Hall, Kyoto, JAPAN
"Electronics Packaging for 5G and B5G"
"IEEE CPMT Symposium Japan (ICSJ)" is one of the most widely recognized international conferences sponsored by the IEEE Electronics Packaging Society (EPS) and has been held annually in Kyoto in November. This conference was inaugurated in 1992 as "The VLSI Packaging Workshop in Japan (VPWJ)" to provide a platform for you to communicate and interact with global leaders in packaging technology. Later in 2010, this conference was renamed to "ICSJ" and ICSJ2021 is the 10th ICSJ meeting, or 19th conference since establishing VPWJ. This year, ICSJ2021 will be a hybrid event of on-site and virtual meetings where several presentation options are available for the authors to select and the details will be announced on the official website at a later date.
-- November 11-12, 2021 (virtual, and in-person in Silicon Valley)
-- Download the Call for Presentations; submit a proposal by 1 September
-- Join the REPP Distribution List for updates