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NEW – Society Member Digital Library

Beginning with the 2023 renewal cycle, EPS members will have access to the new EPS Digital Library! 

This will include online access via Xplore to the Transactions on Components, Packaging and Manufacturing Technology (T-CPMT), EPS sponsored conference proceedings including ECTC, ESTC, ITherm and more! 

Unlimited access to current and past issues of T-CPMT and proceedings for EPS sponsored conferences from current year to the early nineties.

We are pleased to announce our 2022 Electronics Packaging Symposium will take place September 7-8, 2022 at Binghamton University Campus as a live event!! We will be planning a smaller event than we had done in past symposiums as we try to take into consideration those that are still hesitant to travel. The focus of our symposium will be the needs and the challenges of the electronics industry. We will be updating this webpage with the session titles and keynote speakers as we get on with our planning.  We look forward to seeing you in September.

Register here

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The third annual Symposium on Reliability for Electronics and Photonics Packaging (REPP) will be held November 9 ‐10, 2022 at SEMI Headquarters, Milpitas, CA, USA.

REPP’22 is planned to be a hybrid event, with both in‐person and WebEx participation

This symposium will focus on quantified reliability, accelerated testing and probabilistic assessments of the useful lifetime of electronic, photonic, MEMS and MOEMS materials, assemblies, packages and systems in electronics and photonics packaging. This includes failure modes, mechanisms, testing schemes, accelerated testing, stress levels, and environmental stresses.

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With the general trend of miniaturization of electronic devices especially for the Internet of Things (IoT) and implantable medical applications, there is a growing demand for reliable on-chip energy and power sources. Such tiny modules are expected to occupy no more than footprint-sized areas of a few square millimeters so that they can be easily integrated on semiconductor chips, while manufactured and packed using compatible approaches with current semiconductor processing. They are designed to provide power in the range of several µW to hundreds of mW and energy in the range of several hundreds of µWh to several mWh. Along with other emerging power sources such as miniaturized energy harvesters which cannot work alone, various miniaturized on-chip Electrochemical Energy Storage (EES) devices, such as micro-batteries and micro-supercapacitors, have been developed in the last two decades to store the generated energy and respond appropriately at peak power demand. One of the promising designs for onchip EES devices is based on interdigitated three-dimensional (3D) microelectrode arrays, which in principle could decouple the energy and power scaling issues. The purpose of this summary article is to give a generic view of our recent works on designing and manufacturing on-chip miniaturized EES devices in particular 3D EES devices based on carbon microelectromechanical systems (C-MEMS) [1-6]. We also discuss some emerging opportunities in both materials and manufacturing for such applications.

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I.  Introduction

Approximately a trillion transistors could be integrated in a System-in-Package (SiP) (Figure 1) by 2030  by  heterogeneously integrating many CPU, FPGA, AI accelerator, networking, memory, I/O and other chiplets. Chiplet power densities are forecast to increase to 2W/mm2 average with >9W/mm2 hotspots.  SiP performance is limited by the ability to deliver power to and remove heat from the SiP. 

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Congratulations to Dr. Ephraim Suhir, recipient of the 2022 IEEE Santa Clara Valley Section Outstanding Engineer Award "for seminal contributions to several critical IEEE fields, including probabilistic design-for-reliability of microelectronic and photonic materials and systems, and the role of the human factor." 

You can find the most accessed T-CPMT articles on Xplore here

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