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The EPS Awards Program recognizes contributions to the profession, industry and the Society through a comprehensive set of awards and recognitions.

EPS Major Awards

A series of EPS Major Awards, recognizing technical contributions and service, is administered by the EPS Awards Committee:

·       Outstanding Sustained Technical Contribution Award

·       Electronics Manufacturing Technology Award

·       William Chen Distinguished Service Award

·       Exceptional Technical Achievement Award

·       Outstanding Young Engineer Award

·       Regional Contributions Award

 

The Society also sponsors a PhD Fellowship to promote, recognize, and support PhD level study and research within the Electronics Packaging Society’s field of interest.

Awards Nomination Form

PhD Fellowship Nominiation Form 

Nomination Period September 15, 2022- January 21, 2023

Nominations for the 2023 Distinguished Achievement Certificates will be accepted two times per year.

The first round will run from January 1 through June 30 and the second round from August 30 through October 31.

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The EPS proudly congratulates the recently elevated Senior Members and Fellow:

Senior Members                                                   Fellow

Vinod Arjun Huddar                                            Andrew Tay      

Liqiang Cao                 

David Conway                

Fengze Hou           

Jin-Ho Kim            

Ru Li                    

Yang Peng                 

Rene Poelma         

Sandeep Razdan    

Bidyut Sen            

Boris Vaisband                

Geert Van Steenberge    

Teong Guan Yew                

Distinguished Colleagues, Dear Researchers and Scientists,

It is our great pleasure to invite you to submit an extended abstract to the 46th edition of the International Spring Seminar on Electronics Technology from Wednesday May 10th to Sunday May 14th, 2023 organized in Timisoara, The European Culture Capital of 2023  (https://timisoara2023.eu/en/).

The ISSE 2023 conference will feature keynotes from renowned experts and practitioners, oral and poster presentations from outstanding scholars and researchers from academia and industry and will reflect an overview of the most recent developments in electronics packaging technology.

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Over the past two decades, the IEEE Workshop on Signal and Power Integrity (SPI) has evolved into a forum of exchange on the latest research and developments on design, characterization, modeling, simulation and testing for Signal and Power Integrity at chip, package, board and system level. The workshop brings together developers and researchers from industry and academia in order to encourage cooperation.

In view of previous years success, the Committees are hardworking and keen on the 27th Edition which will be held as an in-person event in Aveiro, Portugal from May 7-10, 2023. The technical program will include both oral and poster sessions, and several prominent experts will be giving keynotes on areas of emerging interest.

The Technical Program Committee (TPC) is seeking original and unpublished contributions on all aspects of Signal and Power Integrity. All contributions will undergo a rigorous review process, conducted by the TPC. Instructions for manuscript submission are available in the Submissions menu. Full paper submission date is January 23, 2023.

Feel free to look into our website for further information about IEEE SPI 2023, as well as broadcast the workshop in your institution and to your fellow colleagues and students. It is a pleasure to invite you all to the 27th IEEE Workshop on Signal and Power Integrity and we look forward to your contribution and participation!

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3 – 4th November, Dallas

Dear IEEE 73rd ECTC Attendees,

A group of dedicated industry leaders and top researchers gathered in Dallas and worked over two days to prepare the exciting premier packaging conference in the world: the IEEE Electronic Packaging Society sponsored ECTC 2023. The subcommittees met and created the conference sessions drawing from 618 abstracts received, of which 335 include a first-time ECTC author. We want to thank all authors who submitted their abstracts. Fortunately, we can accommodate the majority of them in our next program; soon, the authors of the selected papers will be notified. Additionally, the executive committee discussed conference details, including the changes to the program. The authors who submitted abstracts this year may have already noticed that we have updated our abstract submission platform. One of the updates is the requirement that the authors provide the novelty of their work and their abstract.

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Electronics Packaging Chapter

Tutorial: Reliability Testing and Design for Reliability of Packaging Interconnects

-- 2-Hour Short Course: lead-free solder joints, power creep, viscoplasticity, temperature, strain rate, constitutive equations, thermal-cycling, examples, recommendations  ...

Speaker: John H Lau, Unimicron Technology Corporation

Date: Thursday, January 5, 2023

Time: Checkin via WebEx at 7:45 AM (PST); Presentation 8:00 – 10:00 AM (PST)

Cost: none

vTools Information: https://events.vtools.ieee.org/m/336536

Registration: https://r6.ieee.org/scv-eps/?p=2996

Summary: Recent advances and trends in lead-free solder joint reliability are presented in this study. Emphasis is placed on the design for reliability (DFR) and reliability testing and data analysis, including: Norton power creep constitutive equations and examples; the Wises two power creep constitutive equations and examples; the Garofalo hyperbolic sine creep constitutive equations and examples; and the Anand viscoplasticity constitutive equations and examples, with temperature and strain rate-dependent parameters. For reliability testing and data analysis, the Weibull and lognormal life distributions for lead-free solder joints under thermal-cycling and drop tests;  the true Weibull slope, true characteristic life, and true mean life; and the linear acceleration factors for various lead-free solder alloys based on frequency and maximum temperature, dwell time and maximum temperature; and frequency and mean temperature will be presented. Some recommendations will also be provided.

Electronics Packaging Chapter

Thermal and Failure Analysis of Advanced Sub-Micron Devices

-- thermal imaging, fine-geometry, static/dynamic, high-resolution, thermoreflectance, near-ultraviolet to infrared, examples ...

Speaker: Dr. Mo Shakouri, Microsanj Corp.

Date: Thursday, January 26, 2023

Location: in person at SEMI World Hdqtrs, Milpitas, CA USA (and via WebEx)

Time: Checkin at SEMI (sandwiches and drinks) at 11:30 AM (PST); Presentation at noon (PST). WebEx at noon.

Cost: none

vTools Information: https://events.vtools.ieee.org/m/336546

Registration: https://r6.ieee.org/scv-eps/?p=2998

Summary: Performance requirements for today’s semiconductor and optoelectronic devices are leading to shrinking geometries, more complex 3-dimensional structures, and new materials. High temperatures, hot spots and temperature spikes can have a major impact on reliability. It is essential that one have a thorough understanding of static and dynamic thermal performance under operating and static conditions. This has traditionally been complex, time consuming, and often lacked the resolution required to detect thermal anomalies that could lead to early device failures. Fortunately, advances in thermal imaging techniques that combine the benefits of thermoreflectance-based analysis with illumination wavelengths from near-ultraviolet to near infrared coupled with infrared thermography can support thermal, spatial, and transient resolution consistent with today’s advanced complex device structures and shrinking geometries. In addition, equipment has advanced to considerably reduce the time and cost to get accurate results. Many examples will be shared to fully illustrate the device thermal behaviors that can be detected with these advanced thermal analysis techniques.

Murali Murugesan†1 , Kristoffer Martinson1 , Amos Nikos1 , Tongchang Zhou1 , Hongfeng Zhang1 , Lars Almhem1 and Johan Liu†2 

1 SHT Smart High Tech AB, Arendals Allé 3, SE-418 79, Gothenburg, Sweden

2 Electronics Materials and Systems Laboratory, Department of Microtechnology and Nanoscience (MC2), 

Chalmers University of Technology, Kemivägen 9, SE-412 96 Gothenburg, Sweden.

Email: murali.murugesan@smarthightech.com and johan.liu@chalmers.se

ABSTRACT

The rapid growth of information technology continues to increase power density and integration levels in electronics devices, leading to an increase in greater heat dissipation, lower performance, and shorter operating life. Thus, the development of new Thermal Interface Materials (TIM) with substantially high thermal conductivity is essential for various device cooling applications. This paper focuses on the development of a new high-performance thermally conductive graphene enhanced TIM (GT-TIM) via chemical cross-linking of vertically aligned graphene and silicone polymer. The effect of vertical alignment on the thermal performance of the new GT-TIM has been evaluated and further potential use in various application areas has been proposed. Advantageously, GT-TIM offers a very low thermal contact resistance at the same time very high elasticity, recovery degree and very high reliability as compared to the state-of-the-art TIM materials available in the market.

INTRODUCTION

There is an increasing demand for efficient thermal dissipation materials with high thermal conductivity, and high elasticity to be used in electronics cooling applications such as 5G wireless modules, high-power CPUs/GPUs, data servers, gaming modules, LEDs, and Opto-modules.1-2 To handle the needs, the industry uses whatever the market can offer and takes higher repair costs, with lower/limited performance to survive and wait for better TIMs to be developed. This indicates that the electronics industry constantly seeks new TIM products to solve thermal management issues. 

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Csaba Farkas, Attila Géczy, Rebeka Kovács, Attila Bonyár, IEEE Senior Member

Department of Electronics Technology, Faculty of Electrical Engineering and Informatics,

Budapest University of Technology and Economics, Budapest, Hungary;

bonyar.attila@vik.bme.hu

Abstract

Biodegradables and nanomaterials are a promising path for the future of electronics in a greener mindset. Biodegradables and nanocomposites are already effectively used in prototypes and advanced application areas with demanding requirements, such as flexible and wearable electronics, implantable or biomedical applications, and traditional commercial electronics. The nano-enhanced biopolymer substrates (e.g., with improved gas and water barrier functionalities) sometimes also with integrated, nano-enabled functionalities (such as electromagnetic shielding or plasmonic activity) can be beneficial in many electronics packaging and nanopackaging applications as well.

1. Introduction

Electronics industry is facing significant problems with increasing production and, consequently, the problem of hazardous electronic waste [1]. The issue is additionally elevated by the global market-based attitude, which encourages consumers to discard outdated hardware. While most of the electronic equipment and modules are essentially non-degradable, proper recycling is also a crucial concern. In the modern time period of the technology, some rules were implemented to prevent the manufacture of devices with hazardous elements (an example: the “RoHS Directive”, which was a key action in this matter more than a decade ago [2-3]).

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The EPS congratulates Guoqi (Kouchi) Zhang, recipient of the 2023 Rao Tummala Electronics Packaging Award, "for scientific and technological leadership in "More than Moore" (MTM) packaging." 

Guoqi Kouchi Zhang

Prof. Zhang made outstanding technical contributions to More than Moore (MtM) packaging, co-designing, and reliability. His technical achievements enabled many key applications including energy saving via LED packaging, IoE via sensor packages, 5G via AiP, and much more. He is one of the persistent leaders of developing co-designing methods that lays down the foundation for designing for reliability, lifetime diagnostics and prognostics, virtual prototyping/qualification, and digital twin of packaging. Zhang developed an accelerated test method for LED systems that substantially reduced testing time. His accelerated test method opened the way to commercialization of LED technology and has been a key technology in reducing global energy consumption. An IEEE Fellow, Zhang is a chair professor at Delft University of Technology, Delft, the Netherlands.

The Rao Tummala Electronics Packaging Award, an IEEE Technical Field Award, sponsored by the EPS and administered by the IEEE Awards Board, is the highest award honoring technical achievement in EPS fields of interest. 

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