IEEE Heterogeneous Integration Roadmap (HIR) Symposium
2nd Annual, intro to HIR v1.0, overviews, integration, working groups, participation …
HIR v1.0 Roadmap Release
Co-hosted by EPS Santa Clara Chapter & SEMI
When: February 21 - 22, 2019
Where: SEMI Headquarters, 673 South Milpitas Blvd, Milpitas, CA
Cost: $25 IEEE/ASME members, students, unemployed; $40 non-members. ($10 more after Feb. 10th) (includes lunch)
Registration waived for HIR Technical Working Group (TWG) members
Thursday, February 21, 2019: HIR Symposium
Time: 8:30 AM – 6:00 PM
Who Should Attend: Open to the General Public
Speakers: Chairs of Working Groups (from Intel, Boeing, Fraunhofer, NASA, Infineon, Google, Advantest, StatsChipPaC, Dow, ASE, ITRI, SEMI, more)
Friday, February 22, 2019: HIR Technical Working Meeting and Open House
Time: 8:30 AM – 4:00 PM
Who Should Attend: All HIR Technical Working Group members and anyone interested in participating or learning more about the Heterogeneous Integration Roadmap.
The purpose is to provide a forum for interaction, collaboration and feedback.
Presenter: Prof. Rao Tummala
Date: February 26, 2019
Time: 10:00 AM ET
Earn 1 Professional Development Hour (PDH) for completing the webinar - Complete Form
This webinar proposes Moore’s Law for Packaging to replace Moore’s Law for ICs, as this is seen as coming to an end. Moore’s Law for ICs is about scaling transistors to ever smaller sizes, from node to node and interconnecting and integrating these to result in more transistors in smaller chips at lower cost from 300 mm wafers. As transistor scaling and integration comes to an end due to physical, material and electrical limitations, Moore’s Law for Packaging (MLP) can be viewed as interconnecting and integrating smaller chips with the highest transistor density and highest performance at the lowest cost. Package or system scaling is proposed to be one and the same, as the end goal of packaging is a system. Just as Moore’s Law for ICs has two components: number of transistors and cost of each transistor, Moore’s Law for Packaging is proposed to have two components as well: the number of interconnections or I/Os and the cost of each I/O. This webinar lays the ground work for Moore’s Law for Packaging by showing how I/Os have evolved from one package family node to the next, starting with <16 I/Os in 1960s to the current silicon interposers with about 200,000 I/Os. It proposes a variety of ways to extend Moore’s Law such as extending Si interposers and beyond, using glass in panel embedding. As Moore’s Law for Electronic Packaging comes to its own end, this article proposes 3D opto-electronic packaging as the next Moore’s Law for Packaging.
The premier international packaging, components, and
microelectronics systems technology conference
The 2019 ECTC includes:
· 41 technical sessions covering all aspects of advanced packaging:
o 36 technical sessions covering wafer-level and fan-out packaging, 2.5D, 3D and heterogeneous integration, interposers, advanced substrate, assembly, materials modeling, interconnections, packaging for high speed and high bandwidth, photonics, flexible and printed electronics.
o 4 interactive presentation sessions
o 1 student interactive presentation session
On 19th Jan 2019, in conjunction of IEEE Malaysia Section’s Annual General Meeting (AGM) at Dorsett Hotel, Putrajaya, Electronics Packaging Society (EPS) Chapter has also taken its opportunity to organize its AGM in the morning session as well. After the successful AGM event in the morning, IEEE Malaysia Section has also organized an appreciation dinner in the same day at the same venue with the same full-house crowd being witnessed as well for the dinner. The event was kick-started with an opening remark by Assoc. Prof. Dr. Fawnizu A. Hussin, who is the newly elected IEEE Malaysia Section Chair for the session of 2019/2020.
Printed Circuit Board
Ask yourself, what is the most fundamental building block of electronics? I propose that interconnects is the answer. Interconnects dominates the subject matter of IEEE Electronics Packaging Society (EPS) publications. So the next question is what the first revolutionary step in evolution of interconnects? It is the printed circuit board.
On my bookshelf, I have a copy of the book by Clyde Coombs titled Printed Circuits Handbook. I have relied on this book as my primary reference since the 1980s. The first line of the second chapter (written by Dr. Hayao Nakahrar), credits Paul Eisler with the invention of printed wiring technology. Fortunately, the inventor of the printed circuit board (PCB) published an autobiography. The inventor of the PCB was Paul Eisler. He was born in Vienna, Austria in 1907 and died in London, England in 1992. His book is titled My Life with the Printed Circuit which was published in 1989, and reading this book explains much about working in electronics and electronics packaging.Read More
High-Performance III-N Devices and Integration Technologies for Advanced System Applications Abstract: Gallium Nitride (GaN) and related III-N materials offer the promise of exceptional levels of performance for RF, microwave, and mm-wave applications, as well as for power conversion and control. This outstanding performance potential is due in large part to the combination of a large band gap with high critical electric field, high carrier mobility and saturation velocity, and the effects of spontaneous and piezoelectric polarization that enable high sheet carrier concentrations to be achieved without extrinsic doping. These features have led to remarkable device performance, ranging from devices with ft/fmax near 500 GHz in ultra-scaled HEMTs to high-power, high-voltage rectifiers and transistors capable of handling voltages well above 1500 V and 10 A by using vertical device architectures on bulk GaN substrates. For these devices to have maximum system-level impact, however, heterogeneous integration with Si-based electronics and compatibility with advanced packaging platforms is needed. In this talk, recent demonstrations of high-performance GaN-based devices for RF through mm-wave applications, as well as for power conversion and control will be described, and novel advanced processing techniques that promise to enable these devices to be heterogeneously integrated with Si and advanced packages while retaining the unsurpassed performance possible with GaN will be discussed.
All participants will receive WebEx details prior to the event. We sincerely hope that you can join us for these special events.
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