Presenter: Prof. Rao Tummala
Date: February 26, 2019
Time: 10:00 AM ET
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This webinar proposes Moore’s Law for Packaging to replace Moore’s Law for ICs, as this is seen as coming to an end. Moore’s Law for ICs is about scaling transistors to ever smaller sizes, from node to node and interconnecting and integrating these to result in more transistors in smaller chips at lower cost from 300 mm wafers. As transistor scaling and integration comes to an end due to physical, material and electrical limitations, Moore’s Law for Packaging (MLP) can be viewed as interconnecting and integrating smaller chips with the highest transistor density and highest performance at the lowest cost. Package or system scaling is proposed to be one and the same, as the end goal of packaging is a system. Just as Moore’s Law for ICs has two components: number of transistors and cost of each transistor, Moore’s Law for Packaging is proposed to have two components as well: the number of interconnections or I/Os and the cost of each I/O. This webinar lays the ground work for Moore’s Law for Packaging by showing how I/Os have evolved from one package family node to the next, starting with <16 I/Os in 1960s to the current silicon interposers with about 200,000 I/Os. It proposes a variety of ways to extend Moore’s Law such as extending Si interposers and beyond, using glass in panel embedding. As Moore’s Law for Electronic Packaging comes to its own end, this article proposes 3D opto-electronic packaging as the next Moore’s Law for Packaging.