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In December 2020, EPS launched a survey sent to EPS members with the objective to get feedback on overall satisfaction with EPS benefits, what resources are important to them, and how they prefer to receive information from the Society.  Nearly 300 of our members responded to this survey, and I’d like to say thank you very much to those of you who provided your thoughts and opinions…your time is very much appreciated!  When this survey was sent to our members, we indicated that we would provide a summary of some of the feedback we received.  The following are a few of the insights we received from the survey that we think will be interesting for our members.

Overall member satisfaction with EPS seems to be very good…77% of respondents indicated they are satisfied or highly satisfied and nearly 90% indicated their intention to renew their EPS membership.  Obviously, these data points indicate there is some opportunity for us to improve (19% were neutral on their EPS satisfaction and nearly 5% were not likely to renew their membership), and so we will continue to work on ways that your EPS membership can provide increased professional, technical, and personal value to you.


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The IEEE Electronics Packaging Society is pleased to announce that it has expanded its Certificate Program to include a new EPS Distinguished Achievement Certificate.  This new level of recognition builds on the initial EPS Achievement Certificate aimed at early-career professionals, and provides a pathway for mid-career to late-career professionals to highlight their more advanced level accomplishments.

Criteria for all Certificates: Must be an IEEE Electronics Packaging Society Member

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The EPS Resource Center is the IEEE Electronics Packaging Society’s online library of webinars, lectures, presentations and more. It includes content specifically for EPS members. With the EPS Resource Center, you have videos from the world’s leading electronics packaging experts at your fingertips. As an EPS member you have free access to webinars, newsletters and conference content. 

Visit the EPS Resource Center to view the latest in electronics packaging. You still have access to the HIR Webinar series in the EPS Webinar Archive.

You can also earn 1 Professional Development Hour (PDH) for completing an EPS webinar on the Resource Center. This can count towards the EPS Certificate of Achievement.

Date: 24- 26, February 2021
Time: 7:30 AM – 12:30 PM PST
Cost: none
Location: On the Internet (via Zoom)

The IEEE’s Heterogeneous Integration Roadmap is 600+ pages of details across all areas of advanced packaging, covering pre-competitive information for industry, working engineers, and academia. It is intended to guide product development over the next decade, with projections out through 2034.

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IEEE-NANO is the flagship IEEE International Conference on Nanotechnology, which has been a successful annual conference since 2001. Recent conferences were in Macau (2019), Cork (2018), Pittsburgh (2017), Sendai (2016), Rome (2015), and Toronto (2014). Due to the COVID-19 pandemic, the IEEE-NANO 2020 was held virtually.

The conference scope spans both nanoscience and nanotechnology, including:

  • Nanoscale interconnections
  • Flexible and hybrid electronics
  • Power management, energy storage and harvesting
  • Nanomaterials for RF to THz, metasurfaces, plasmonics
  • High-power and High-Reliability packaging
  • Bioelectronic packaging
  • Package modeling at nanoscale

Conference Dates: July 28th to 30th of 2021.

Abstract Submission: February 28th 2021

Submission of 4-page Manuscript to proceedings: May 1st 2021

Abstracts can be submitted at: https://2021.ieeenano.org/authors/abstract-submission-for-review/

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Title:Holistic Understanding  of Thermo-Mechanical challenges  from Package to System  to Maximize Silicon Performance

Presenter: Gamal Refai-Ahmed

Date and Time: March 4th at 3:00 PM EST 

Register Here

Abstract: This presentation is addressing  the impact of the assembly and manufacturing technology and direction on the advancing packaging Mechanical integrity and its thermal characterizations. In this talk, the audiences will  be able to see clearly  the full picture to answer the question of will Lidded or Lidless Advanced Packaging have better Thermo-Mechanical Characteristics?. The answer to this question needs to have a full understanding of the manufacture and assembly, materials behavior, the cost, the mechanical stresses, the end user application and the target thermal performance.  It is not a surprise to find a wrong direction can impact the package performance and lose more than 30% to 50% of its performance.

Title: Trends and Challenges for Electrical Design and Analysis Using Advanced Packaging 

Presenter: Dr. Kemal Aygun

Date: March 17, 2021 11:00 AM EDT

Register Here

Abstract: As the electronics industry is going through some rapid changes, the new electronics systems need to provide increasingly higher performance. As a result, the capability of the components that constitute these systems needs to also scale accordingly. One area where the pace of innovation has greatly increased in recent years is semiconductor packaging. Paving the way for heterogeneous integration, these new ‘advanced’ packaging technologies aim to integrate multiple logic, memory, and other specialized silicon dies, potentially using different silicon process technologies, and provide unprecedented levels of performance in metrics such as IO bandwidth, bandwidth density, and power efficiency. This presentation will review some of these new advanced packaging technologies such as fan-out wafer/panel level and 2.xD packaging and the key challenges and some solutions for their electrical design and analysis.

For a limited time, the Best Papers from ECTC 2020 will be available as open access

1) Best Session Paper
InFO_SoW (System-on-Wafer) for High Performance Computing
Shu-Rong Chun, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chuei-Tang Wang, Jeng-Shien Hsieh, Tsung-Shu Lin, Terry Ku, Douglas Yu - Taiwan Semiconductor Manufacturing

2) Best Interactive Presentation Paper
Embedded 3D-IPD Technology based on Conformal 3D-RDL: Application for Design and Fabrication of Compact, High-Performance Diplexer and Ultra-Wide Band
Ayad Ghannam, Alessandro Magnani, David Bourrier, Thierry Parra - 3DiS Technologies

3) Outstanding Session Paper
10 and 7 µm Pitch Thermo-Compression Solder Joint, Using a Novel Solder Pillar and Metal Spacer Process
Jaber Derakhshandek, Giovanni Capuz, Vladimir Cherman, Funnihiro Inoue, Inge De Preter, Lin Hou, Pieter Bex, Carine Gerets, Fabrice Duval, Thomas Webers, Julien Bertheau, Stefaan Van Huylenbroeck, Alain Phommahaxay, Ehsan Shafahian, Geert Van der Plas, Eric Beyne, Andy Miller, Gerald Beyer - IMEC

4) Outstanding Interactive Presentation Paper
Processing Glass Substrate for Advanced Packaging Using Laser Induced Deep Etching
Rafael Santos, Jean-Pol Delrue, Norbert Ambrosius, Roman Ostholt, Stephan Schmidt - LPKF Laser & Electronics AG

5) Intel Best Student Session Paper
A Comprehensive Study of Electromigration in Lead-free Solder Joint
Jiefeng Xu, Chongyang Cai, Vanlai Pham, Ke Pan, Huayan Wang, Seungbae Park - Binghamton University

The naming of new technologies can be difficult and often inaccurate.  Over time, standards are developed and language becomes aligned. 

The cost of leading-edge nodes, combined with the lack of scaling of significant design blocks (ex:  analog) and die sizes reaching reticle size, is driving disaggregation (splitting up) of chip functions into their best price/performance nodes requiring new technologies to interconnect these functions.  

We are voicing our support in naming these small IP blocks “chiplets”.  It is not a perfect name but fits into our vernacular well and is gaining acceptance in our industry.  Our definition of “chiplet”, and what it is not, follows.  

We appreciate your inputs. 

David McCann

VP EPS Technology


Chiplet is not a package type, it is part of a packaging architecture. It is an integrated circuit block that has been specifically designed to communicate with other, similar chiplets, to form larger more complex ICs. Thus, in large and complex chip designs the design is subdivided into functional circuit blocks, often reusable IP blocks, called "chiplets", that are manufactured and recombined on high density interconnect.

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The Cisco Global Cloud Index estimates that total data center traffic (all traffic within or exiting a data center) will reach almost 20 zettabytes per year by 2021, up from 7 zettabytes in 2016. Data center traffic on a global scale will grow at a 25 percent CAGR, with cloud data center traffic growth rate at 27 percent CAGR or 3.3-fold growth from 2016 to 2021.

The growth in internet traffic not only accelerates the need for next-generation technology to support higher port density and faster speed transitions but is also accompanied by large physical data center sizes as well as faster connectivity between the data centers. As the data rates and distances to carry high speed data are increasing, the limitations of traditional copper cable and multimode fiber-based solutions are becoming apparent and the industry focus is shifting towards adoption of single-mode fiber-optic solutions.

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