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The ITherm 2020 Virtual Conference will be held July 21-23. ITherm 2020 Virtual is packed with many live and recorded activities. Registration fees for the virtual conference are greatly reduced from previous years, and include access to all virtual live and recorded events and an electronic copy of the conference proceedings. 

Join us from 12:00-4:00 PM Eastern on July 21st-23rd for daily live events including: 3 Keynote Talks addressing the future of the 3D system integration technology, ethics in AI, and thermal management challenges of aircraft electrification; an Invited Presentation by the recipient of the Richard Chu ITherm Award for Excellence, 3 Technology-Talk sessions providing deep dive talks on high profile topics; and the returning joint ASME K-16 / IEEE EPS Student Design Challenge on additive manufacturing of heat sinks, sponsored by GE. Recorded events will be available from July 21st till August 19th, and include over 180 technical papers in 50 sessions in 4 Technical Tracks; 60+ Student Posters as a highly engaging forum on the latest research; a joint ECTC/ITherm Diversity Panel and Heterogeneous Integration Roadmap workshop.

ITherm CONFERENCE: https://www.ieee-itherm.net/itherm/conference/home

ACCESS TO MATERIALS: Live streaming and on-demand recordings through the ON24 virtual conference environment

LIVE STREAMING HOURS: 12:00 PM – 4:00 PM (EDT), July 21-23, 2020

CONFERENCE RECORDINGS: Available until August 18, 2020

REGISTRATION OPEN NOW: http://www.cvent.com/d/knq090

The Electronics System-Integration Technology Conferences (ESTC) is the premier European conference on Electronics System-Integration and Packaging, forming together with ECTC and EPTC IEEE EPS’s “flagship conferences”. A biannual event since 2006, ESTC 2020 will be hosted by University of South-Eastern Norway (USN) in Vestfold. Vestfold is the “Electronic Coast” of Norway, hosting the major industry cluster in the nation for high-end electronics, particularly for aerospace, medical, maritime and industrial applications. Due to COVID-19 travel restrictions, ESTC 2020 will be carried out 100% virtual, live! The live format will allow interaction similar to an in-person conference. The digital format will give new possibilities, such as recording of presentations allowing to catch up presentations in parallel sessions.

Registration is now open (https://www.estc-conference.net/estc-2020/registration-1) with a deadline of 10 August. The registration fee is a fraction of the normal conference registration fee. 

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Title: Overview of the Co-Design Chapter of the Heterogeneous Integration Roadmap

Date: July 23, 2020

Time: 11:00 AM EDT - Register Here

Presenters: Professor José Schutt-Ainé and Professor Rohit Sharma


This talk focuses on current state-of-the-art, challenges and potential solutions for Co-Design. Electrical, thermal, and mechanical interactions across the chip-package-board domains can no longer be ignored. New modelling and simulation tools must accurately predict the physical (e.g. electro-thermal, thermo-mechanical, etc) coupling between multiple semiconductor components and the package/system that contains them. The Co-Design Chapter of the Heterogenous Integration Roadmap explores how design and analysis practices need to be defined in the context of heterogeneous integration. It addresses the traditional chip-package-board design flow as well as current capabilities and future challenges. The vision is to create an environment where design closure is achieved with a minimum number of iterations meeting all requirements for performance and cost. This environment must leverage from currently available technologies, namely computing power, algorithms and artificial intelligence.

Download HIR Chapter 13 Co-Design for Heterogeneous Integration

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Title: Additive Manufacturing of Electronic Systems: RF to THz

Dr. Premjeet (“Prem”) Chahal, Michigan State University, East Lansing, MI, USA

Date: Thursday, July 16, 2020, Time: 5:00 - 6:30 PM (PDT) 

Registration Link:https://meetings.vtools.ieee.org/m/234716 

Abstract: Additive manufacturing (AM), often referred to as 3D printing, is a process of building parts layer by layer rather than using traditional molding or subtractive methods. It is revolutionizing how critical parts get manufactured, fast prototyping, reduced waste, allows custom designs, easier design adjustments, and parts can be printed as a single unit. Once employed purely for prototyping, AM is now increasingly used for spare parts, small series production, and tooling. With recent advances in print resolution, the ability to print multiple materials simultaneously, and the ability to print low- and high-temperature materials have opened the opportunity to design and manufacture the next generation of electronic systems. We are investigating AM to realize high-functional density high-frequency systems by integrating different device technologies within a single unit through a continuous build-up process. The process includes integrating active and passive elements, signal and power distribution, optics, MEMS, and thermal cooling and isolation, etc. Novel prototyping materials, additive manufacturing strategies, and heterogeneously integrated 3D compact systems have been developed and demonstrated by our lab. This talk will present examples of high frequency circuits (RF to THz) fabricated using AM in our lab, and key advantages and disadvantages of AM for RF systems integration will be highlighted. 

Bio: Dr. Premjeet (“Prem”) Chahal received the B.S. and M.S. degrees in electrical engineering from Iowa State University, Ames, IA, USA, and the Ph.D. degree in electrical engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 1999. He was a Senior Researcher with Raytheon, Dallas, TX, USA, from 1999 to 2006, and Abbott Laboratories, Abbott Park, IL, USA, from 2006 to 2008, where he developed many new technologies for sensing, devices, packaging, and components. He joined Michigan State University, East Lansing, MI, USA, in 2009, as a Faculty Member, where he has been an Associate Professor since 2015. He has authored more than 150 refereed technical publications and holds nine U.S. patents. His current research interests include terahertz & millimeter-wave electronics, RF-based sensors, RF MEMS, RF-optical devices, and microwave and millimeter-wave systems packaging. Dr. Chahal was a recipient of the 2012 DARPA Young Faculty Award and the 2016 Withrow Teaching Excellence Award.

Note: WebEx URL will be sent out on July 15, 2020 evening to those who register before the event.

Title: Adding a New Sensing Dimension to Soft Electronics: From the Skin to Below the Skin

Dr. Sheng Xu, UCSD, San Diego, CA, USA

Date: Wednesday, August 12, 2020, Time: 5:00 - 6:30 PM (PDT) 

Registration Link: https://meetings.vtools.ieee.org/m/233758

Abstract: Soft electronic devices that can acquire vital signs from the human body represent an important trend for healthcare. Combined strategies of materials design and advanced microfabrication allow the integration of a variety of components and devices on a stretchable platform, resulting in functional systems with minimal constraints on the human body. In this presentation, I will demonstrate a wearable multichannel patch that can sense a collection of signals from the human skin in a wireless mode. Additionally, integrating high-performance ultrasonic transducers on the stretchable platform adds a new third dimension to the detection range of conventional soft electronics. Ultrasound waves can penetrate the skin and noninvasively capture dynamic events in deep tissues, such as blood pressure and blood flow waveforms in central arteries and veins. This stretchable platform holds profound implications for a wide range of applications in consumer electronics, sports medicine, defense, and clinical practices.

Title: Heterogeneous Integration - why is it becoming such a big deal and how does it affect electron device development

Date: 22 July 2020 

Time: 11:00 AM EDT - Register Here

Presenter: Subramanian S. Iyer


If you take any printed circuit board (PCB) today, it is already more than likely an example of heterogeneous Integration.So in truth, Heterogeneous Integration is not really new. So why this new found hype ? In this talk, we describe what needs to be different about heterogeneous integration by trying to address some key differences between the new heterogeneous integration and the ones of bygone eras: What is the optimal size of chiplets or more correctly dielets; what is the optimal pitch at which they need to be connected; How close must we connect them; and how large should we make such integrated units and finally what are the possible showstoppers as we boldly march into this new era. An important implication for those working in the device and integration area: don't kill yourself trying to put everything on one mega chip. It's getting more and more difficult and expensive. We can get equivalent or better results in most cases using heterogeneous dielet integration at fine pitch and close spacing. As they say " small is beautiful and vive la difference!"


Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. More recently, he has been exploring new packaging paradigms and architectures that they may enable including in-memory analog compute and medical engineering applications. He has published over 300 papers and holds over 75 patents. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.



The International Spring Seminar on Electronics Technology (ISSE) is one of the renowned conferences encompassing all topics around electronics technology and is attended every year by more than 100 experts and young researchers from all over the world.  This year's event, the 43rd in the ISSE series, was planned to be held in Hotel Grand Jasna, in the beautiful Demanovska Valley - Slovakia, Europe - https://isse2020.fei.tuke.sk.  However, due to the Corona pandemic which came over Europe in last March we decided to organize this event as a web-based conference, since the abstract submission, the review process, and a draft of the conference technical program was already completed at that time. The change from the usual mode of a four-day event with personal attendance with an extensive cultural program to a two-day online conference with a condensed technical program was a big one.

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