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In June 2021, the first IEEE Student Branch was established at Addis Ababa Institute of Technology, Addis Ababa University in Addis Ababa, Ethiopia. The IEEE EPS Santa Clara Section (Chair: Annette Teng) from Northern California played a critical role by being a big brother and providing the financial support to start the branch 3000 miles away. We would also like to thank Dr. Fetene Mulugeta, from the School of Electrical and Computer Engineering, for serving as the faculty advisor of the "IEEE Addis Ababa University Student Branch.” This and similar student branches will play key roles in IEEE EPS conferences to be held on the continent of Africa.

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Title: Second Phase and IMC Variation of Solder Joint under Eelctromigration

Date: July 16th, 2021

Time: 9am -10am (New York) / 9pm-10pm (Taipei)

Presenter: Prof. Kwang-Lung Lin, Department of Materials Science and Engineering, National Cheng Kung University

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Abstract: The solder joint, due to its shrinking dimension between the joined items, experiences high current density during application. The athermal electromigration force in combining with the Joule heat will cause a variety of variations to the relatively small dimension solder joint. This talk will present and discuss the effect of electromigration on the recrystallization of second phase and IMC, the effect of current direction on the interfacial IMC formation, and the transformation of IMC under electromigration in solder joint.

Title: Advanced Packaging for Autonomous Driving

Date:July 27, 2021 (Tuesday)

Time:10.00am – 11.00am (M’sia Time, GMT +8:00) 

PresenterDr. Eu Poh Leng

 

Abstract: Great business opportunities in many industries are made available due to the advancement in autonomous driving technology, driven by automotive megatrends.  Architecting the autonomous car requires comprehensive system solutions with safety and security built in.  Car electronics packaging are changing to meet the higher functional requirements. New package types emerges as a result of greater innovation.  The future of packaging is definitely more exciting!

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Title: Ultrafast Time Domain Cryogenic CMOS Device Characterization Platform for Quantum Computing Applications 

Date: September 30, 2021 

Time: 12:00 pm PDT/3:00 pm EDT

Presenter: Pragya Shrestha, NIST

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You can earn 1 Professional Development Hour (PDH) for attending this webinar by completing the PDH survey form

Title: Ultrafast Time Domain Cryogenic CMOS Device Characterization Platform for Quantum Computing Applications

Date: September 30, 2021

Time: 12:00 pm PDT/3:00 pm EDT

Presenter: Pragya Shrestha, NIST

Register here

You can earn 1 Professional Development Hour (PDH) for attending this webinar by completing the PDH survey form

 

Abstract: Cryogenic electronics have a wide range of applications, ranging from quantum information science to extra-terrestrial electronics to gravitational wave research to high performance computing. However, the dominant application leading the way for cryogenic electronics research, is quantum computing where electronic functionality at the 4 K or below has become a requirement. The most promising candidate to fulfil this functionality without disturbing the cryogenic environment with a path to large-scale integration is CMOS. Therefore, a lot of effort has been put in to hunt for the right CMOS device technology and obtain their low temperature models for designing reliable and accurate cryogenic circuits.  Though it has been acknowledged that precise characterization is crucial for reliable low power and low temperature circuit design, obtaining reliable device characterization and reliability at low temperatures has not been sufficiently addressed. Absent specially is the time domain characterization of devices which are crucial for designing accurate analog circuitry. This webinar will review the challenges of using cryogenic CMOS in the field of quantum computing and further discuss the motivation for creating cryogenic ultra-fast time domain device characterization setup for accurate high-performance cryogenic CMOS circuit design.

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Symposium on Reliability for Electronics and Photonics Packaging

 Reliability, Failure Modes and Testing for Integration of Electronics and Photonics (SiPh)

1112 November 2021    Silicon Valley, CA  USA

REPP’21 is planned to be a hybrid event, with both inperson and WebEx participation

This symposium will focus on quantified reliability, accelerated testing and probabilistic assessments of the useful lifetime of electronic, photonic, MEMS and MOEMS materials, assemblies, packages and systems in electronics and photonics packaging.  This includes failure modes, mechanisms, testing schemes, accelerated testing, stress levels, and environmental stresses.

The intent is to bring together electrical, reliability, materials, mechanical, and computer engineers and applied scientists to address the stateoftheart in all the interconnected fields of electronic and photonic packaging, with an emphasis on various reliabilityrelated aspects: designforreliability, manufacturing, reliability modeling and accelerated testing.

Proposals for presentations in the fields of Reliability for Electronic and Photonic

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IEEE International 3D System Integration Conference

November 15-18, 2021

This year’s IEEE International 3D System Integration Conference (3DIC 2021) will be a hybrid physical/virtual event.  The live conference will be held at North Carolina State University in Raleigh, NC.  The virtual conference will be held concurrently.  Authors and attendees can choose either format to interact with 3D researchers from all around the world.

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IEEE EPS Malaysia: 2021 Technical Talk on Autonomous Driving

Dr Eu Poh Leng who is the Director of External Package Innovation in NXP Semiconductors, as well as the Vice Chairman of IEEE EPS Malaysia Chapter, was invited as a Keynote Speaker in the recent Symposium by Yole Development and NCAP on Advanced Packaging for Semiconductors (SYNAPS).  In view of the Covid-19 pandemic situation, SYNAPS was held virtually for participants all over the world.  The event took place over 3 half-days from 18th to 20th of May 2021, with 3 different categories of topic each day:

           Day 1: Heterogeneous Integration

           Day 2: Fan Out and SiP

           Day 3: Emerging Package and Performance

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You can find the most accessed T-CPMT articles on Xplore here