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Term 1 January 2022 through 31 December 2024


The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members at Large will be selected each year to represent the regional composition of the Society membership.

Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG.  The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect members-at-large from within their Region only (that is, members in Regions 1-7 & 9 vote for Members-at-Large from Regions 1-7 & 9, members in Region 10 vote for Members-at-Large from Region 10).


Candidates for Member-at-Large must:

  • a current members of both IEEE and EPS
  • willing to attend two annual Board meetings
  • willing to participate actively in areas of their interest (publications, conferences, membership development, chapter development, etc.)

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The IEEE Electronics Packaging Society is pleased to announce that it has expanded its Certificate Program to include a new EPS Distinguished Achievement Certificate.  This new level of recognition builds on the initial EPS Achievement Certificate aimed at early-career professionals, and provides a pathway for mid-career to late-career professionals to highlight their more advanced level accomplishments.

Criteria for all Certificates: Must be an IEEE Electronics Packaging Society Member

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If you have been involved in the electronics packaging field for 10 years or more, chances are that you probably already have the necessary qualifications to be an IEEE Senior Member.  Senior membership is the highest IEEE membership grade that can be applied for and is a recognition of sustained and significant performance in an IEEE-designated field.  Individuals who are IEEE members can apply themselves for elevation to Senior Member or they can be nominated by others.  Since a member can be nominated by someone else for Senior Membership, Society Chapters can play an important role in helping to identify and support applications for elevation.  Nominating individuals in our Chapters is a great way to recognize their professional achievements and foster deeper personal and professional relationships with our peers.  Individual members shouldn’t hesitate to apply for Senior Member elevation on their own as well, and call upon their IEEE colleagues for support for their application.

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In our April EPS Newsletter, we proposed a definition of chiplets.  Please see the EPS website:

Definitions - IEEE Electronics Packaging Society

This has generated continuing interest within EPS and with external groups, specifically around what is most needed to support chiplet technology adoption, what should our role be in supporting that adoption, and how should we support adoption?

1.     What is most needed?  We believe that standards, particularly for interconnect architecture and test, are what is most needed to drive widespread adoption of chiplets into products.

2.     Our role:  Our role in EPS is to support standards organizations to help drive successful chiplet technology adoption.  We are not a standards organization and will not be driving a standard on our own.  We encourage our members to participate in existing standardization efforts. 

3.     How can we best support standard development and adoption?   OCP (Open Compute Project) has initiated the ODSA (Open Domain-Specific Architecture) industry effort to draft a specification for chiplet interconnect that could then become a standard over time.  We have also started discussion with JEDEC and linked JEDEC to the ODSA project to explore if JEDEC can take a leading role in driving a chiplet standard.

Visit the ODSA website at the address below to better understand their project and needs:


If you are interested in supporting the ODSA effort, you can contact Lei Shan at:


David McCann, EPS VP Technology

Abstract— The rapid adoption of 5G mobile networking technology means that packaged ICs have new features and capabilities that present significant test challenges. IC package test requires quick adaptations to address these new test challenges. In this paper we discuss some of the key areas that need innovation to address these test challenges as volume of 5G IC’s rapidly scale. This increases the demand for the development of low cost and scalable high-volume manufacturing test solutions. We discuss the challenges in OTA test, tooling and interconnects, and RF test instruments.

Keywords—5G, mmWave, package test, OTA, RF, Test Instruments, DFT, near field, modulation, sockets, interconnects


As we shift into the new decade, the world is quickly becoming more connected and 5G proliferation is playing a key role. Many aspects and industries are embracing the value of 5G including automotive, health care, the cloud, and creating opportunities for smart homes and cities [1][2]. 5G enabled IC’s are at the center of this evolving infrastructure.

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Title: Sintered Silver As Die Attach Materials

Date: 6-July-2021 (Tue)

Time: 10.00am – 11.00am (Maylasia)

Platform: IEEE CISCO WebEx

Speaker: Dr. Siow Kim Shyong

·       Senior Member IEEE, CEng (IOM3), MIMMM, PMP, MATRIZ Lvl3,

·       Research Fellow / Senior Lecturer, Institute of Microengineering and Nanoelectronics, Universiti Kebangsaan Malaysia

·       IEEE CPMT Malaysia Chairperson from Y2014-2016

Moderator: Chua SK, Infineon

Registration: Coming soon!!!!


Please check out our website for registration details


This talk introduces the motivation for using sintered silver (Ag) as die-attach material and associated processes used in forming this Ag joint in bonding application. In addition, the talk also addresses the main factors influencing the mechanical properties (die shear strength) of the Ag joint, namely, sintering temperature, pressure, time, heating rate, atmosphere, substrate metallization and its roughness, and die-size. Comparison with sintered Cu is also included in this talk. This talk is expected to be useful to those new to this die attach materials and interested to explore this bonding technique further in their process.

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IEEE-EPS Malaysia Chapters AGM – 6th Feb 2021

This year IEEE-EPS Malaysia Chapters held their AGM 100% through webinar. Please join me in congratulating the incoming IEEE Electronic Packaging Society Malaysia Section committee that is led by Dr Yik Yee Tan from ON Semiconductor.


for Undergraduate Final Year Project

The winner of this award is Tain Yuan Phin from University Tunku Abdul Rahman (UTAR) supervised by Ts. Dr. Karen Wong Mee Chu from Department of Mechanical & Materials Engineering. 

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You can find the most accessed T-CPMT articles on Xplore here