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Term 1 January 2022 through 31 December 2025

NOMINATION DEADLINE EXTENDED:  30 June 2022

The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members at Large will be selected each year to represent the regional composition of the Society membership.

Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG.  The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect members-at-large from within their Region only (that is, members in Regions 1-7 & 9 vote for Members-at-Large from Regions 1-7 & 9, members in Region 10 vote for Members-at-Large from Region 10).

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Nomination form

Title:  Chiplet Design and Heterogeneous Integration Packaging

Presenter: John Lau

Date: July 5, 2022

Time: 8:00 AM EDT

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Abstract:

In this lecture, chiplet design and heterogeneous integration packaging are defined. Examples such as those given by Xilinx, AMD, Intel, TSMC, and Samsung will be presented and discussed. The lateral communication between chiplets such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound as well as flexible bridges will be presented. UCIe (universal chiplet interconnect express) will also be updated. Key enabling technologies such as thermocompression bonding and hybrid bonding will be briefly mentioned. The trends and challenges (opportunities) of chiplet design and heterogeneous integration packaging will be discussed.

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PSMA and IEEE EPS invite you to attend the Fourth Biennial International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM-23). This Symposium brings synergistic advances in component design and integration combined with 3D manufacturing technologies – customized to different market segments such as computing, automotive industry, energy sector, and low-power medical and wearables systems.This Symposium provides the opportunity to share progress in design, active and passive components, and integration combined with 3D manufacturing technologies for power electronics packaging.

The Symposium will be held February 1-3, 2023, at Florida International University, Miami, FL, USA., offering an opportunity to get a “winter warm-up” on Florida’s enticing beaches.

Created and supported by the PSMA’s Packaging & Manufacturing Committee, 3D-PEIM will feature invited papers highlighted by plenary and keynote addresses and contributed presentations by Industry and Academia experts. Speakers will address mechanical, materials, reliability, and manufacturability issues. There will be Exhibits and an Exhibit Sponsor’s Session.

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International Workshop on Integrated Power Packaging (IWIPP 2022)

 

Registration is now open for IWIPP 2022, a PSMA and IEEE sponsored hybrid workshop. The event will be held August 24-26, 2022, at the World Trade Center in Grenoble, France, and hosted by G2Elab. IWIPP is a growing and successful power technology workshop with excellent speakers and networking opportunities.

Register here

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For a limited time, the Best Papers from ECTC 2021 will be available as Open Access

1)      Best Session Paper
  Proof of Concept: Glass-Membrane Based Differential Pressure Sensor
Anatoly Glukhovskoy - Leibniz University, Maren S. Prediger - Leibniz University, Jennifer Schäfer- Leibniz University, Norbert Ambrosius - LPKF Laser & Electronics AG, Aaron Vogt - LPKF Laser & Electronics AG, Rafael Santos - LPKF Laser & Electronics AG, Roman Ostholt - LPKF Laser & Electronics AG, and Marc Christopher Wurz - Leibniz University

2)      Best Interactive Presentation Paper 
  System in package embedding III-V chips by fan-out wafer-level packaging for RF applications
Arnaud Garnier, Laetitia Castagné, Florent Gréco, Thomas Guillemet, Laurent Maréchal, Mehdy Neffati, Rémi Franiatte, Perceval Coudrain, Stéphane Piotrowicz, and Gilles Simon - CEA-Leti. Authors 1-3, 7, 8, 10: CEA-Leti, Author 4: Thales DMS, Authros 5, 6: United Monolithic
Arnaud Garnier - CEA-Leti, Laetitia Castagné - CEA-Leti, Florent Gréco - CEA-Leti, Thomas Guillemet - Thales DMS, Laurent Maréchal - United Monolithic Semiconductors, Mehdy Neffati - United Monolithic Semiconductors, Rémi Franiatte - CEA-Leti, Perceval Coudrain - CEA-Leti, Stéphane Piotrowicz - III-V Lab, Gilles Simon - CEA-Leti

3)      Outstanding Session Paper
 Ultra-Thinning of 20 nm-Node DRAMs down to 3 um for Wafer-on-Wafer (WOW) Applications
Zhiwen Chen - Tokyo Institute of Technology, Naoko Araki - Tokyo Institute of Technology, Youngsuk Kim - Tokyo Institute of Technology, Tadashi Fukuda - Tokyo Institute of Technology, Koji Sakui - Tokyo Institute of Technology, Tomoji Nakamura - Tokyo Institute of Technology, Tatsuji Kobayashi - Micron Memory Japan, Takashi Obara - Micron Memory Japan, and Takayuki Ohba - Tokyo Institute of Technology 

4)      Outstanding Interactive Presentation Paper 
  Cu Recrystallization and the Formation of Epitaxial and Non-Epitaxial Cu/Cu/Cu Interfaces in Stacked Blind Micro Via Structures
T. Bernhard, S. Dieter, R. Massey, S. Kempa, E. Steinhäuser, F. Brüning. All authors: Atotech Deutschland GmbH.

5)      Intel Best Student Session Paper
  Mechanical Behavior and Reliability of SAC+Bi Lead Free Solders with Various Levels of Bismuth
KM Rafidh Hassan, Jing Wu, Mohammad S. Alam, Jeffrey Suhling, and Pradeep Lall. All authors: Auburn University

I.INTRODUCTION

Universal Chiplet Interconnect Express (UCIe)® [1] is an open industry standard interconnect, offering high-bandwidth, low-latency, power-efficient, and cost-effective on-package connectivity between chiplets. It addresses the compute, memory, storage, and connectivity needs across the entire compute continuum, spanning cloud, edge, enterprise, 5G, automotive, high-performance computing, and hand-held segments. UCIe offers a plug-and-play interconnect at the package level, enabling a designer to package chiplets from different sources, including different fabs, using a wide range of packaging technologies. 

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Abstract —Modern 5G, Internet of Things (IoT), and wearable devices require tons of features packed into a small, portable form factor. This brings significant challenges to both the design of the packaging and the manufacturing of the device. This is where additive manufacturing (AM) can play a critical role. AM is a technology which can deposit various of materials in both 2D and 3D manner to realize complex geometries with superior resolution, accuracy, and speed. Compared to traditional subtractive manufacturing methods such as milling and chemical etching, AM techniques only use the minimum amount of materials which can reduce the cost significantly, making it the ideal candidate for future “smart city” that promises to connect billions of devices in all different types of environments. AM also enables novel integration of structures that are un-realizable with traditional manufacturing techniques. With AM, fully featured electronic devices can be realized in a customized 3D multi-layer stack within a single package. This paper gives a review of additively manufactured highly integrated packaging structures that operate at 5G mm-wave frequencies.

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Nanopackaging can be defined as the packaging of devices and systems with nanoscale materials, structures, designs and process integration for improved performance, miniaturization, functionality, reliability and cost. Nanopackaging seeks to bridge the gap between nanoscale ICs,  and the rest of the milliscale and microscale system components. Furthermore, all major aspects of future system integration: improved functional density, higher power densities and power efficiency, higher bandwidth with lower power, improved thermal management, sensor fusion and integration, and better reliability rely on Nanopackaging. These examples are illustrated in Fig. 1. ECTC 2022 showcased some of the nanotechnology advances that have been systematically addressing the challenges associated with heterogeneous integration. This newsletter article describes these advances in the respective categories. 

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The EPS President Kitty Pearsall (left) presents the Region 6 Chapter of the Year Award 2021 to the SCV/OEB/SF EPS chapter.  Accepting the award are Chandan Bhat, Chapter Secretary (center) and Annette Teng,Chapter Chair  during 2021 (right) on May 26, 2022 at SEMI Headquarters in Santa Clara. "Best Chapter on the West Coast!"

                      SCV Region 6 Presentation Chapter of the Year Award 2021                                        Outstanding chapter award to Santa Clara Valley