Title: Chiplet Design and Heterogeneous Integration Packaging
Presenter: John Lau
Date: July 5, 2022
Time: 8:00 AM EDT
In this lecture, chiplet design and heterogeneous integration packaging are defined. Examples such as those given by Xilinx, AMD, Intel, TSMC, and Samsung will be presented and discussed. The lateral communication between chiplets such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound as well as flexible bridges will be presented. UCIe (universal chiplet interconnect express) will also be updated. Key enabling technologies such as thermocompression bonding and hybrid bonding will be briefly mentioned. The trends and challenges (opportunities) of chiplet design and heterogeneous integration packaging will be discussed.