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On February 21, 2019, the second annual HIR Symposium was held at SEMI Headquarters in Milpitas, CA.

The symposium was a success, attracting more than 190 registrants. The EPS Santa Clara Valley Chapter and SEMI sponsored the symposium. The IEEE Electronics Packaging Society, IEEE Photonics Society, IEEE Electron Devices Society, SEMI and ASME/EPPD sponsor the Heterogeneous Integration Roadmap. The symposium featured talks from the various Technical Working groups as well as a plenary talk from Dr Babak Sabi, Corporate Vice President, Intel).  Invited speakers included Ajit Manocha, SEMI CEO, Rolf Aschenbrenner, Fraunhofer and Dr. Nicky Lu, Chairman & CEO of Etron Technology, Inc. and Managing Board Director, Taiwan Semiconductor Industry Association (TSIA).
There was representation from industry, Academia, Government and Research Institutes.
The list of some of the institutions represented included Google, Microsoft, IBM, Cisco, Western Digital, Ford, Microsoft, Apple, Corning, Lockheed Martin, Boeing, Intel, AMD, Xilinx, NVIDIA, Broadcom, TI, Wolfspeed, TSMC, GLOBALFOUNDRIES, Samsung Electronics (Device), MicroSemi, Tower Jazz, Analog Devices, Rambus, ASE Group, JCET, Flex, Promex, Sypnosys, Cadence, Mentor Graphics, Dow Dupont, Namics, Heraeus, Advantest, Teradyne,  Fraunhofer (Germany), ITRI (Taiwan), PARC, NASA Ames, iNEMI, UC Santa Barbara, Arizona State, U Santa Clara, and Binghamton University.
 
On February 22, the Heterogeneous Integration Roadmap held a Technical Working Group caucus for roadmap members and anyone who was interested to collaborate, network and exchange ideas. The Technical Working Groups expect to release the first version of the Roadmap by early May.

HIR photo1HIR phot 2

In order to further the education of Electronics Packaging Society (EPS) members, the EPS is now offering a Certificate Program. The goal of the program is to give members new to electronics packaging an opportunity for further packaging education, offer continuous education in electronics packaging to existing members, and also to offer students electronics packaging training if they are in a University program that does not include packaging education.

Criteria: Must be an IEEE Electronics Packaging Society Member

To receive your certificate, 15 professional development hours (PDHs) must be completed. This can be obtained from a combination of the following:

1). IEEE EPS Webinar (1 PDH) – must complete PDH evaluation

2). Professional Development Courses – must complete survey and CEU credit form. Previous PDCs from the last 10 years can be used towards this if  the CEU application was completed at the time of the course.

- Electronic Components and Technology Conference (USA)  = 4 PDHs

- Electronic Systems-Integration Technology Conference (Europe) = 3 PDHs

- Electronic Packaging Technology Conference (Asia) = 4 PDHs

3). Author of IEEE T-CPMT and/or EPS conference paper(s) (5 PDHs) – paper must be published in IEEE Xplore within the last 5 years.

4). Reviewer for IEEE T-CPMT (3 Reviews = 5 PDH) within the last 5 years.

Once you have completed any combination of the above and received 15 PDHs, please complete the certificate form to request your Electronics Packaging Society Certificate.

Congratulations to these EPS Members on receiving the IEEE Certificate of Achievement from the IEEE Electronics Packaging Society and completing the required number of professional development hours.

Jinto George, University of Sherbrooke

Arkaprovo Das,  Simyog Technology Pvt. Ltd.

Chuan Seng Tan, Nanyang Technological University

Koushik Ramachandran, GLOBALFOUNDRIES

Jonas Zuercher, ESPROS Photonics AG

David Dahl, Hamburg University of Technology

 

In January, the EPS Program Director - Chapters, Kitty Pearsall dropped in to tour the Mechanical Department at the HKUST and ran into two members of the EPS Hong Kong Chapter. Jeffrey Lo and EPS Past President, Ricky Lee were excited to share their banner and windbreakers displaying their support of EPS at HKUST.

HongkongHongKong2

Based on the latest Submission-to-ePublication Report (4th auarter 2018 report), T-CPMT has reduced the number of Average Weeks Submitted to Online Post from 33 (2nd quarter 2018 report) to 23.5 weeks.

The IEEE Transactions on Components, Packaging and Manufacturing Technology now has a Letters section within the publication. Papers will be a maximum of 4 pages and relate to the research and application on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.  The intent of the Letters section is to enable the rapid dissemination of the latest information in topics of interest to the readership of the IEEE Transactions on Components, Packaging and Manufacturing Technology and thus improve dialog across the community.

The technical content of papers must be both new and significant.

Manuscript Length: The standard length for an accepted Letters manuscript must not exceed 4 pages. The 4th page is reserved exclusively for references in order to accommodate a comprehensive reference list of pre-published and to-be-published articles with full authors’ names, title, and DOI (where available). 

When submitting your Letters into ScholarOne, select "Letters" as paper type.

Template for Letters in Transactions

3-D Printed Metal-Pipe Rectangular Waveguides

Mario D’Auria ; William J. Otter ; Jonathan Hazell ; Brendan T. W. Gillatt ; Callum Long-Collins ; Nick M. Ridler ; Stepan Lucyszyn

Publication Year: 2015, Page(s):1339-1349 

 

An Electrohydrodynamic Jet Printing System With Metal Nanoparticle-Based Ink: Experimental Evaluation

Jung Woo Sohn ; Chulhee Han ; Chun-Yong Park ; Seung-Bok Choi

Publication Year: 2019, Page(s):343-352

 

Composite Glass-Silicon Substrates Embedded With Microcomponents for MEMS System Integration

Bin Luo ; Mengying Ma ; Ming-Ai Zhang ; Jintang Shang ; Ching-Ping Wong

Publication Year: 2019, Page(s):201- 208

 

Novel Electronic Packaging Method for Functional Electronic Textiles

Menglong Li ; John Tudor ; Jingqi Liu ; Russel Torah ; Abiodun Komolafe ; Steve Beeby

Publication Year: 2019, Page(s):216-225

Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration

Takafumi Fukushima ; Arsalan Alam ; Amir Hanna ; Siva Chandra Jangam ; Adeel Ahmad Bajwa ; Subramanian S. Iyer

Publication Year: 2018, Page(s):1738 - 1746

 

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Dan Donahoe

IEEE Senior Member

 

In my introduction to this column, I promised to write about engineering in terms of the parable of the blind man and the elephant. I claimed that business and economics is one of these viewpoints, and I wrote the following paragraphs to support that claim.

In the figure below, I plotted productivity (Gross Domestic Product, GDP) data provided by Bradley DeLong in his Estimates of World GDP, One Million B.C. – Present.  Note that the GDP is in 1990 dollars. 

Economists have determined that productivity through almost all of human history has primarily been determined by population size. This economic rule by population size was true until the advent of the Industrial Revolution which introduced labor-enhancing machinery. Since it takes time for any newly introduced technology to “diffuse” from isolated usage to widespread adoption throughout society, the productivity rise over succeeding years evolution after the Industrial Revolution likely reflects that diffusion.

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There is a new IEEE Future Directions initiative: IEEE Quantum.

If you are interested in becoming involved as an EPS member, please let us know -  email EPS

More information is available on the IEEE Quantum website