March 2020

The 3^rd Annual Heterogeneous Integration Roadmap (HIR) meeting, Symposium and Workshop, held on February 20-21, 2020 at SEMI world headquarters, Milpitas, CA was a resounding success. The two day event, co-organized by IEEE EPS, EPS Santa Clara Valley Chapter and SEMI, was held to celebrate the release of the HIR 2019 edition released on October 10^th and to kick-off the preparation of the HIR 2020 edition. The HIR Symposium on February 20^th featured presentations from all 22 Technical Working Groups (TWG).  They were complemented by two plenary speakers. Dr. Predeep Dubey from Intel Parallel Computing Lab spoke on “Virtuous Cycle of AI” and Dr. Hong Liu from Google Infrastructure spoke on “The Role of Optics on Computing”. The HIR Global Advisory Council members, Ajit Manocha gave the opening remarks in the morning, and Nicky Lu did the wrap-up in the afternoon. The TWG collaboration workshop agenda on February 21^st  started with a “Chiplet on the Rise Forum” with two speakers: Bapi Vinnakota from ODSA and  David Kehlet from Intel. This was followed by TWG collaboration sessions for the HIR 2020 edition preparation. The total attendance of more than 180, included representatives from all 22 TWG teams as well as participation from a broad cross-section from the electronics industry, academia, government and research institutes, demonstrating the increasingly high interest and crucial relevancy in the Heterogeneous Integration Roadmap. The two day event was sponsored by Google, Cisco, Intel, Promex, ASE Group, Samsung, Silitronics, together with SEMI & IEEE EPS.  

Download the Roadmap here

We invite you to be among the first to have your article peer-reviewed and published in the new Electronics Packaging section within IEEE Access. This is an exciting opportunity for your research to benefit from the high visibility of IEEE Access.  Your work will also be exposed to 5 million unique monthly users of the IEEE Xplore® Digital Library.

The Electronics Packaging Section within IEEE Access will draw on the expert technical community to continue IEEE’s commitment to publishing the most highly-cited content. The Journal peer-review process targets a publication period of 6 weeks for most acceptecd papers. This journal is fully open and compliant with funder mandates, including Plan S. 

Scope

The IEEE Electronics Packaging Society section in IEEE Access covers the scientific, engineering, and production aspects of materials, components, modules, hybrids and micro-electronic systems for all electronic applications, which includes technology, selection, modeling/simulation, characterization, assembly, interconnection, packaging, handling, thermal management, reliability, testing/control of the above as applied in design and manufacturing. Examples include optoelectronics and bioelectronic systems packaging, and adaptation for operation in severe/harsh environments. Emphasis is on research, analysis, development, application and manufacturing technology that advance state-of-the-art within this scope.

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EuroSimE 2020 Cracow is postponed to Sunday July 05th to Wednesday 08th.

Considering the fact that many people are unable to travel for an unknown period of time, because of corporate directives, the EuroSimE Steering Committee decided to postpone the event to July 5^th-8^th. As a results, the deadlines for registration are shifted as well. On top of that, we also allow for submission of new abstracts.

Speakers: the deadline for you to register and post final papers is now May 31. It is possible to submit new abstracts until May 08.

Follow www.eurosime.org for updates on the conference.

ECTC 2020 IEEE EPS Seminar: May 28, 2020

Chair

  Yasumitsu Orii, NAGASE & CO., LTD.

  Shigenori Aoki, LINTEC Corporation

 “Future Semiconductor Packages for AI hardware”

An overwhelming amount of data is generated daily, out which 90% is unstructured. Such data cannot be easily stored in a traditional column-row database, therefore, it is not easily searchable and more difficult to analyze. Today, artificial intelligence (AI) has the ability to analyze unstructured data, however, it also require a high amount of energy. AI is expected to become one of the biggest energy consumers on the planet. A brain-inspired devices and quantum devices are very attractive to support a future AI due to its low power consumption. In this session, the panelists will discuss the future semiconductor packages in the era of a brain-inspired devices and quantum devices.

Rama Divakaruni, IBM T. J. Watson Research-Albany, “Future of Innovation - IBM AI Hardware Center”

Hiroyuki Akinaga, The National Institute of Advanced Industrial Science and Technology (AIST), “Brain-inspired ReRAM Devices for AI-edge Computing”

Subramanian S. Iyer, UCLA, “Why all this hype about Heterogeneous Integration ?”

Takashi Hisada, IBM Research-Tokyo, “Heterogeneous Integration for IBM AI Hardware”

Madhavan Swaminathan, Georgia Institute of Technology,  ”Intelligent Digital and RF Convergence for AI”

The Electrical Design, Modeling, and Simulation technical committee of the Electronics Packaging Society (EPS) addresses the electrical aspects of package and system design. The TC name is descriptive of the scope of issues of interest to the members. The committee strives to balance the industry and academic participation to guide the members of the EPS society in this area. The TC chairs are Dr. Dale Becker, IBM, Prof. Stefano Grivet-Talocia, Politecnico di Torino, and Prof. Rohit Sharma, IIT Ropar.

Recently, EDMS has initiated a joint industry – academic effort to establish a “Package Benchmark Suite.” This effort is chaired by Dr. Fei Guo of AMD and Prof. Ali Yilmaz of UT-Austin and has about 15 active participants. Initial package designs are nearing availability through this effort to represent signal distribution and power distribution. Dr. Kemal Aygun presented a detailed overview of this effort as a session and led a productive planning meeting in October 2019 at the EPEPS conference in Montreal.

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