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Title 1: Flip Chip Die Attach Fluxes from Industry Perspective

Title 2: Reliability Issues Related to No-clean Flux

Date: 22nd Mar 2022 (Tuesday)

Time: 10.00am – 11.30am (M’sia Time, GMT +8:00)

Platform: CISCO WebEx

Presenter 1: Mr. Azham Mohd Sukemi

Presenters 2: Prof. A. S. M. A. Haseeb, Mr. Saif Wakeel (2 speakers)

Title 1 Abstract:

Flux is a crucial element in flip chip attach (FCA) process as its performance directly influences reliability of a package.  In this presentation, the significance of FCA flux and issues associated with flux residue will be addressed briefly.  The selection of flux type (Clean vs. Non-Clean) and the reason of why industry prefers one type over the other will also be discussed.

Title 2 Abstract:

The complexity of cleaning of miniaturized, high density electronic packages and the drive towards cost reduction have recently led to an increasing interest in no-clean fluxes (NCF).  However, chemically induced reliability issues related to no-clean flux residues remain a serious concern.  The first part of this talk gives an overview on the typical chemical constituents of NCF, their compositional ranges and functions. In the second part, our recent research results on the characterization and performance of two commercial no-clean fluxes in fine pitch flip-chip package are presented. Comparison is also made with a commercial water soluble flux (WSF). Results show that the NCF treated flip chip packages offer improved wetting and die pull strength of solder bumps after reflow, compared with those treated by the WSF. However, the NCF treated packages perform poorly in moisture sensitivity and temperature cycling tests. Attempt is made to understand the relationship between the characteristics of the fluxes, their performance in flip chip packages and failure mechanisms.

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*E-certificates will be provided to all participants

-To Chiplet or Not To Chiplet: Heterogeneous Integration and Chiplets – March 24, 2022

-The Future of Hardware Technologies for Computing – March 24, 2022

For more information, or to join our Dlist, visit https://ieee.org/scveps.

For 50 years, the number of transistors that could be squeezed onto a piece of silicon had increased on a predictable schedule known as Moore’s law. However, the Moore’s law is reaching to the end. The new approach comes with “chiplets” which is something like high-tech Lego blocks. Instead of carving new processors from silicon as single chips, semiconductor companies assemble them from multiple smaller pieces of silicon—known as chiplets. We will discuss the several interconnect technologies for Chiplets such as Silicon Bridge, Advanced Interposer, Fan-out wafer-level packaging, and optical interconnection. We will have 6 panelists and each panelist will prepare a short set of slides to present within 10-15 minutes, followed by panel discussion. The Special Seminar will be on June 2, 2022 at 8:00pm – 9:30pm. 

ECTC is open for registration at ECTC | IEEE Electronic Components and Technology Conference.   

Please click here for details on the panel.

Muhannad S. Bakir, mbakir@ece.gatech.edu

In recent years, the field of packaging has taken center stage as the semiconductor industry pursues ever more energy efficient, high-performance, and low-cost electronic systems. While the field of packaging is undergoing revolutionary technology advances today, there is little doubt that packaging in the new era of Moore’s Law will offer extreme levels of die integration/bonding and begin to blur the boundary between on- and off-chip connectivity (especially in 3D architectures) due to ever denser physical I/O interfaces/bonds. This new form of ‘packaging’ is often referred to as ‘Heterogeneous Integration’ or HI today. A common goal for HI is to enable the interconnection of multiple dice (or “chiplets”) of various functionalities in a manner that approaches monolithic-like performance yet utilizes advanced off-chip interconnects and packaging/assembly to provide flexibility in IC fabrication and design, improved scalability, reduced development time, and reduced cost. In fact, a cost-benefit analysis of monolithic die disaggregation was recently performed at the 3 nm node and showed that chiplets become cost competitive when monolithic die size exceeds 150 mm2 due to yield considerations of larger monolithic die [1].

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MEPTEC will be hosting the next Road to Chiplets free virtual event focused on the best-known methods (BKM) of Heterogeneous Integration Testability on March 15 and 16 from 8 to 11 am Pacific. Register today to not miss as properly implementing testability features in the design and having a robust test strategy is essential to make Chiplets commercially viable.

Topics to be covered include: Overview of HI Testability, Chip to Chip Test Interfaces, Test Economics, Protocol Based Testing, Die Probing Strategies, OSAT Challenges, and more. Presenters include experts who contributed to IEEE Electronic Packaging Society (EPS) Test Technology Council’s (TTC) recently released “Heterogeneous Integrated Product Testability Best-Known Methods (BKM)” and other industry experts.

Please see the full agenda and register now to attend for free.

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