Bridge-chip Interconnect Technologies
Muhannad S. Bakir, mbakir@ece.gatech.edu
In recent years, the field of packaging has taken center stage as the semiconductor industry pursues ever more energy efficient, high-performance, and low-cost electronic systems. While the field of packaging is undergoing revolutionary technology advances today, there is little doubt that packaging in the new era of Moore’s Law will offer extreme levels of die integration/bonding and begin to blur the boundary between on- and off-chip connectivity (especially in 3D architectures) due to ever denser physical I/O interfaces/bonds. This new form of ‘packaging’ is often referred to as ‘Heterogeneous Integration’ or HI today. A common goal for HI is to enable the interconnection of multiple dice (or “chiplets”) of various functionalities in a manner that approaches monolithic-like performance yet utilizes advanced off-chip interconnects and packaging/assembly to provide flexibility in IC fabrication and design, improved scalability, reduced development time, and reduced cost. In fact, a cost-benefit analysis of monolithic die disaggregation was recently performed at the 3 nm node and showed that chiplets become cost competitive when monolithic die size exceeds 150 mm2 due to yield considerations of larger monolithic die [1].