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A Message from the ECTC General Chair, Dr. Chris Bower

We are excited to bring you the 70th ECTC as a free digital experience.

Due to the global pandemic, which continues to impact all of our lives, the 70th ECTC has transformed into an online virtual conference. Thanks to the tremendous logistical support from our sponsoring organizations and from the generous financial support from our corporate sponsors, we are able to provide the virtual conference at no charge to anyone who wishes to attend. The technical program will look familiar to anyone who has attended an ECTC. The conference will include over 350 technical papers organized into 45 topical sessions, where each session will be available as an on-demand webcast for the duration of the conference, which will open on Wednesday, 3 June and close on Tuesday, 30 June. Beyond the technical sessions, the conference will include a keynote presentation from Dr. Douglas Yu of TSMC, and six special sessions with presentations by invited experts from around the world.

To learn more about the conference go to the ECTC website and join the ECTC LinkedIn group. We hope that everyone will be excited about this unique, no-cost, opportunity to receive the latest updates on the most important topics in microelectronic packaging. If you have not already done so, please register for the 70th ECTC here.

Thank you to all of the authors, speakers and ECTC volunteers. It is your hard work that makes ECTC a premier, high-quality, technical conference.

Dr. Chris Bower
70th ECTC General Chair
X Display Company
Email: chris@xdisplay.com

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Heterogeneous Integration Roadmap (HIR), released October 2019, is a roadmap to the future of electronics identifying technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration between industry, academia and government to accelerate progress. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of Emerging Research Devices and Emerging Research Materials with longer research-and-development timelines. With the release of the 2019 HIR edition, the preparation of the 2020 edition is well underway.

This HIR workshop at ECTC 2020 will feature speakers from all 22 chapters in 4 separate sessions together with an HIR overview presentation. They will describe their work in HIR 2019 and their focus for HIR 2020. The purpose of the HIR workshop is to broaden the proliferation of the roadmap content to the virtual ECTC 2020 participants for dialogue and feedback for inclusion into the 2020 edition.

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The Electronics System-Integration Technology Conferences (ESTC) is the premier European conference on Electronics System-Integration and Packaging, forming together with ECTC and EPTC IEEE EPS’s “flagship conferences”. A biannual event since 2006, the Executive Committee is proud to welcome to ESTC 2020 in Vestfold, bringing ESTC for the first time to Norway. Vestfold is the “Electronic Coast” of Norway, hosting the major industry cluster in the nation for high-end electronics, particularly for aerospace, medical, maritime and industrial applications. Closely collaborating with this industry cluster, Vestfold also hosts University of South-Eastern Norway (USN), organizing ESTC 2020 together with IEEE-EPS. Last but not least, Vestfold is the centre of Viking cultural heritage.

ESTC 2020 can promise a very interesting programme, with 108 oral presentations and 54 interactive poster presentations. Highlights of the programme include:

5 keynotes:

Autonomous Shipping: Lars Kristian Moen, Kongsberg Maritime, Norway

Quantum Computing with Near-Term Devices: Andreas Fuhrer, IBM Zurich, Switzerland

Agriculture 4.0: Development of Smart Sensors Systems for Sustainable Food Production: Alan O'Riordan, Tyndall National Institute, Cork, Ireland

Fan-out Wafer and Panel Level Packaging and the Changing Packaging Landscape: Tanja Braun, Group Manager Fraunhofer IZM Berlin, Germany

Using Artificial Intelligence Methods to Ensure Electronics System Reliability: Michael Pecht, Director of CALCE, University of Maryland, USA

Special session - The end of Moore's Law; the future is bright:

Post Moore's Law and Quantum  Electronics: Rao Tummala, PRC, Georgia Institute of Technology, USA

Can Matter Waves Save Moore?: Bodil Holst, University of Bergen, Norway

Heterogeneous Integration Roadmap (HIR) session: Organized by William Chen, ASE Group, USA

Current COVID-19 restrictions limits the possibility for conference organization with on-site participation. What travel restrictions will apply in September, is not possible to predict at the moment. The Executive Committee is therefore happy to offer digital participation for those that cannot travel to Norway. Further details of how the conference will be carried out, will be announced in June.

On behalf of the Executive Committee,

Knut E. Aasmundtveit                                 Kristin Imenes                                              Paul Svasta

University of South-Eastern Norway           University of South-Eastern Norway           CETTI, Romania

General Chair                                                        Executive Chair                                                    Technical Program 

The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members at Large will be selected each year to represent the regional composition of the Society membership and one Member at Large will be selected to represent the Young Professional community. A Young Professional is an individual that has completed their first academic degree within the last 15 years.

Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG.  The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect members-at-large from within their Region only (that is, members in Region 8 vote for Members-at-Large from Region 8, members in Region 10 vote for Members-at-Large from Region 10; etc.)

The Young Professional Member at Large will be elected by all members of the Society from a slate that is finalized by the Nominations Committee. 

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We are announcing another webinar in the HIR webinar series

Title: Thermal Management Challenges and Opportunities for Heterogeneous Packages

Date: May 27, 2020

Time: 11:00 AM EDT - Register Here

Presenter: Dr. Madhu Iyengar and Mehdi Asheghi

Earn 1 Professional Development Hour (PDH) for completing an EPS webinar - Complete Form


In response to a growing awareness of thermal challenges related to Heterogeneously Integrated Packages, a Thermal Technical Working Group has focused on trends for cooling requirements, known technical solutions, and advanced concepts and research covering three areas, namely, the die level, the package integration/SIP/module level, and to a lesser extent the system Level (limited to board level). This webinar covers two primary thermal aspects related to heterogeneous integration: (a) definition of canonical problems and thermal challenges, and (b) active research areas and results, which have been the focus of the published 2019 roadmap chapter.  The canonical problems have included: 2D chip with stacked memory on a silicon/glass interpose, 3D stacked die with conduction interfaces, 3D stacked die with embedded liquid cooling, optics/photonics cooling, thermal management for harsh environment (military, aerospace, automobile), mobile applications, and voltage Regulators. The research and advance cooling advances encompass Thermal Interface Materials, liquid cooling, single and two-phase liquid cooling, air cooling, materials, and modeling. The talk will also touch upon an ongoing effort for the 2020 chapter related to recent roadmap discussions around memory cooling, silicon micro-channels, and photonics cooling.


Madhu Iyengar is a Senior Staff Engineer at Google and a lead with technical and managerial responsibilities for innovative product development and path-finding for IT hardware and physical infrastructure, including chip packages, server systems, and data centers.  As Chief Engineer since 2015, he has led Google’s chip-to-data center liquid cooling research and product development program, yielding the delivery of a breakthrough liquid-cooled high performance Machine Learning IT System that has been globally deployed at scale.  Previously, he has worked at Facebook, IBM, Purdue University's Cooling Technology Research Center, and Kirloskar Oil Engines.  He has a PhD in Mechanical Engineering from the University of Minnesota.  Madhu has served as an Associate Editor for the ASME Journal of Electronic Packaging, the IEEE CPMT Transactions and the ElectronicsCooling Magazine, a voting member of the ASHRAE TC9.9 Mission Critical Facilities committee, and as the General Chair of the 2016 ITherm Conference.  He has co-authored over 115 technical papers in journals, conference proceedings and book chapters, edited 1 book, and holds 280 US patents.  He is currently the Chair for the Thermal Technical Working Group for the IEEE Electronics Packaging Society Roadmap effort on Heterogeneous Integration.  Madhu is an elected Fellow of the American Society of Mechanical Engineers.  His contact is miyengar@google.com.

Adjunct Professor Mehdi Asheghi was a founding member of the Stanford Nanoheat Laboratory as a graduate student back in 1994.  He completed his Ph.D. and postdoctoral studies at Stanford through research on nanoscale thermal engineering of microelectronic devices, including several highly cited papers on phonon conduction in silicon layers. He led a very well funded research program at Carnegie Mellon University (2000-2006) that focused on nanoscale thermal phenomena in semiconductor and data storage devices. At Stanford his research ranges from nanoscale memory technologies to two phase microfluidics.  Dr. Asheghi is the author of more than 200 journal publications,fully-reviewed conference papers, and book chapters, and was technical program and  general chairs at ITHERM 2012, 2014 and InterPACK 2015 and 2017, respectively.  Mehdi is a member of theThermal Technical Working Group (TWG) of the IEEE EPS HIR initiative.

Download HIR Chapter 20 Thermal

More webinars will be scheduled:

June 18, 2020 HIR Chapter 2: High Performance Computing and Data Centers

July 1, 2020 HIR Chapter 17: Test Technology

The reliability TC meet every quarter on Webex and a face to face meeting every year at ECTC conference.  The following are the major missions and visions of the reliability TC.

Identify the current reliability challenges

Advanced packaging technologies

Advanced materials/interconnects

Advanced packaging assembly processes

Package board and advanced Si BEOL/FEOL interactions

Develop the reliability roadmap on emerging technologies/devices/materials in 5 and 10 years

IC Component and System - with the HIR (Heterogeneous Integration Roadmap) Task Groups

Si – with IRDS TWGs

SiC/GaN/GaAs/InP -  with Wide Bandgap Roadmap; Ask for expert in SiC/GaN; EPOSS in Europe

Organize seminars/workshop and work with the major conferences to cover the challenging reliability issues


The following PDCs have been conducted at EPTC 

·       EPTC2018, Advanced Integrated Circuit Design for Reliability, Dr. Richard Rao

·       EPTC2019, Reliability Mechanics and Modeling for IC Packaging - Theory, Implementation and Practices, Prof. Xuejun Fan, Lamar University

The committee has identified the following challenging reliability issues and will schedule webinars to address each of these topics.

Multi physics and multi scale interactions

Thermal, mechanical and electrical

Chip to package to board interaction mechanisms

Chip, package and system Reliability co-design/simulation

Advanced 2.5D/3D/2.x D IC and Si Photonics packages with new materials and multiple critical interfaces

GPU/CPU/FPGA with advanced Si/packaging to meet stringent automotive reliability targets

Si nodes beyond 5nm – new FET architecture/material/process/interface characterization

Reliability testing- With the silicon process and package process/material change dramatically, current JEDEC long term reliability standard need to be updated

If you are interested in joining the committee or want to know more information, please contact the following individuals.

Dr. Richard Rao, rrao@inphi.com, Reliability TC Chair, USA

Dr. Xueren Zhang, XUERENZ@xilinx.com, Reliability TC Co-Chair, Asia

Dr. Gromala Przemyslaw Jakub, PrzemyslawJakub.Gromala@de.bosch.com, Reliability TC Co-Chair, Europe

This is an exciting opportunity for your research to benefit from the high visibility of IEEE Access. Your work will also be exposed to 5 million unique monthly users of the IEEE Xplore® Digital Library.

The Electronics Packaging Section within IEEE Access will draw on the expert technical community to continue IEEE’s commitment to publishing the most highly-cited content. Our goal is to publish quickly - the rapid peer review process has demonstrated an average submission to publication time of 5.0 weeks.  This journal is fully open and compliant with funder mandates, including Plan S.


The IEEE Electronics Packaging Society section in IEEE Access covers the scientific, engineering, and production aspects of materials, components, modules, hybrids and micro-electronic systems for all electronic applications, which includes technology, selection, modeling/simulation, characterization, assembly, interconnection, packaging, handling, thermal management, reliability, testing/control of the above as applied in design and manufacturing. Examples include optoelectronics and bioelectronic systems packaging, and adaptation for operation in severe/harsh environments. Emphasis is on research, analysis, development, application and manufacturing technology that advance state-of-the-art within this scope.

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EPEPS is the premier international conference on advanced and emerging issues in electrical modeling, measurement, analysis, synthesis, and design of electronic interconnections, packages, and systems. It also focuses on new methodologies and CAD/design techniques for evaluating signal, power, and thermal integrity and ensuring performance in high‐speed, RF, and wireless designs. EPEPS is jointly sponsored by IEEE Electronics Packaging Society, IEEE Microwave Theory and Techniques Society and IEEE Antennas and Propagation Society.

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Prof. Tummala of Georgia Tech publishes the most comprehensive and up–to-date Undergrad and Introductory packaging textbook, with all the Latest Device and Systems Packaging Technologies. 

Undergrad and  introductory Textbook- "Fundamentals of Device and System Packaging: Technologies and Applications” edited by Prof Tummala, published and available from Amazon and McGraw-Hill. 

For decades, Moore's Law has driven the semiconductor technology advancements.  As Moore’s Law for IC’s comes to an end due to physical, material, electrical and financial limitations, this book goes on to propose Moore’s Law for Packaging through advanced interconnections at IC and system levels. In the first chapter Prof. Tummala explains the device packaging concept and its evolution from microelectronics to  RF and wireless,  followed by photonics and MEMS and Sensors  eventually leading to quantum devices. He describes the shift in industry focus from transistors to interconnections at the system level enabled by heterogeneous integration in 2D, 2.1D, 2.5D and 3D packages. 

Prof. Tummala introduces the concept of Moore’s Law for Packaging or interconnections (MLP) that cab be viewed as interconnecting and integrating smaller chips with the highest transistor density and highest performance at the lowest cost. Just as Moore’s Law for ICs has two components -- the number of transistors and cost of each transistor -- Moore’s Law for Packaging is  proposes to have  two components as well: the number of interconnections or I/Os and the cost of each I/O. This book lays the groundwork for all the elements required to extend Moore’s Law to packaging, not only at device level but. At system level.  

This book introduces 16 essential core packaging technologies at system level. Each technology is detailed in its own chapter.  These include electrical, mechanical, and thermal design, materials and processes for electronic, photonic, wireless to 5G and to millimeter-wave, I/O interconnections and assembly to organic, Si and wafer-level packages, passive components, sealing and encapsulation, and board design and assembly.  Once these 16 building block technologies are explained, the book moves on to application of these  packaging technologies  and architectures  for autonomous driving, bioelectronics, communication systems, computer systems, flexible electronics and smartphones – dedicating a chapter to each of these applications. Nowhere else can one find a more comprehensive explanation of the fundamentals and applications of electronics packaging described in a single volume. The homework problems and recommended reading at the end of each chapter are other attributes of the book. It is the ideal undergraduate and introductory  textbook to prepare future packaging engineers, or  anyone interested in a deeper understanding of the  packaging technology. 

The book was authored and edited by Prof Rao  Tummala ,with contributions from  57 of the world’s leading experts from Intel, IBM, TI, Global Foundries, Sanmina, and many others, as well as Prof Tummala’s colleagues at Georgia Tech., UCLA, KAIST(Korea), Michigan State, Chinese Academy of Sciences, TU Dresden  and his students at Georgia Tech.

Author: Eric Perfecto