We are announcing another webinar in the HIR webinar series
Title: Thermal Management Challenges and Opportunities for Heterogeneous Packages
Date: May 27, 2020
Time: 11:00 AM EDT - Register Here
Presenter: Dr. Madhu Iyengar and Mehdi Asheghi
Earn 1 Professional Development Hour (PDH) for completing an EPS webinar - Complete Form
In response to a growing awareness of thermal challenges related to Heterogeneously Integrated Packages, a Thermal Technical Working Group has focused on trends for cooling requirements, known technical solutions, and advanced concepts and research covering three areas, namely, the die level, the package integration/SIP/module level, and to a lesser extent the system Level (limited to board level). This webinar covers two primary thermal aspects related to heterogeneous integration: (a) definition of canonical problems and thermal challenges, and (b) active research areas and results, which have been the focus of the published 2019 roadmap chapter. The canonical problems have included: 2D chip with stacked memory on a silicon/glass interpose, 3D stacked die with conduction interfaces, 3D stacked die with embedded liquid cooling, optics/photonics cooling, thermal management for harsh environment (military, aerospace, automobile), mobile applications, and voltage Regulators. The research and advance cooling advances encompass Thermal Interface Materials, liquid cooling, single and two-phase liquid cooling, air cooling, materials, and modeling. The talk will also touch upon an ongoing effort for the 2020 chapter related to recent roadmap discussions around memory cooling, silicon micro-channels, and photonics cooling.
Madhu Iyengar is a Senior Staff Engineer at Google and a lead with technical and managerial responsibilities for innovative product development and path-finding for IT hardware and physical infrastructure, including chip packages, server systems, and data centers. As Chief Engineer since 2015, he has led Google’s chip-to-data center liquid cooling research and product development program, yielding the delivery of a breakthrough liquid-cooled high performance Machine Learning IT System that has been globally deployed at scale. Previously, he has worked at Facebook, IBM, Purdue University's Cooling Technology Research Center, and Kirloskar Oil Engines. He has a PhD in Mechanical Engineering from the University of Minnesota. Madhu has served as an Associate Editor for the ASME Journal of Electronic Packaging, the IEEE CPMT Transactions and the ElectronicsCooling Magazine, a voting member of the ASHRAE TC9.9 Mission Critical Facilities committee, and as the General Chair of the 2016 ITherm Conference. He has co-authored over 115 technical papers in journals, conference proceedings and book chapters, edited 1 book, and holds 280 US patents. He is currently the Chair for the Thermal Technical Working Group for the IEEE Electronics Packaging Society Roadmap effort on Heterogeneous Integration. Madhu is an elected Fellow of the American Society of Mechanical Engineers. His contact is email@example.com.
Adjunct Professor Mehdi Asheghi was a founding member of the Stanford Nanoheat Laboratory as a graduate student back in 1994. He completed his Ph.D. and postdoctoral studies at Stanford through research on nanoscale thermal engineering of microelectronic devices, including several highly cited papers on phonon conduction in silicon layers. He led a very well funded research program at Carnegie Mellon University (2000-2006) that focused on nanoscale thermal phenomena in semiconductor and data storage devices. At Stanford his research ranges from nanoscale memory technologies to two phase microfluidics. Dr. Asheghi is the author of more than 200 journal publications,fully-reviewed conference papers, and book chapters, and was technical program and general chairs at ITHERM 2012, 2014 and InterPACK 2015 and 2017, respectively. Mehdi is a member of theThermal Technical Working Group (TWG) of the IEEE EPS HIR initiative.
More webinars will be scheduled:
June 18, 2020 HIR Chapter 2: High Performance Computing and Data Centers
July 1, 2020 HIR Chapter 17: Test Technology