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 Term 1 January 2024 through 31 December 2026


Nomination Form

The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members at Large will be selected each year to represent the regional composition of the Society membership.

Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG.  The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect members-at-large from within their Region only (that is, members in Regions 1-7 & 9 vote for Members-at-Large from Regions 1-7 & 9, members in Region 10 vote for Members-at-Large from Region 10).

The Young Professional Member at Large will be elected by all members of the Society from a slate that is finalized by the Nominations Committee. 

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T-CPMT provides the latest information in electronics packaging.  Contribute to the research in the electronics packaging field by becoming an IEEE peer reviewer. Peer reviewers fulfill a vital role in the publishing process by giving detailed and professional commentary.

If you are interested in becoming a reviewer, please update (or create) your account on the  T-CPMT ScholarOne submission site   (https://mc.manuscriptcentral.com/ieee-tcpmt).

It is especially important to indicate your areas of expertise with several keywords.  These keywords will be accessed by Associate Editors searching for reviewers in the database, based on the keywords of the submissions received. Feel free to also send an email to alert us of your availability to review, and we will pass on your account information to the Associate Editors in charge of new manuscript submissions that match your area.

We recognize that quality reviews are extremely important and take significant effort on behalf of the peer reviewing volunteer community. The average review time for a T-CPMT paper is less than 7 days.  Although all reviewers remain anonymous during the review process, all reviewers are named and acknowledged annually in the December issue.

EPS Executive Office: Denise Manning d.manning@ieee.org

EPS VP Publications: Ravi Mahajan ravi.v.mahajan@intel.com

12th IEEE CPMT Symposium Japan November 15 – 17, 2023,

Venue: Ritsumeikan University Suzaku Campus, Kyoto, JAPAN (On-site only)

 "Advanced Packaging for Chiplet Era"

“IEEE CPMT Symposium Japan (ICSJ)” is one of the most widely recognized international conferences sponsored by the IEEE Electronics Packaging Society (EPS) and has been held annually in Kyoto in November. This conference was inaugurated in 1992 as “The VLSI Packaging Workshop in Japan (VPWJ)” to provide a platform for you to communicate and interact with global leaders in packaging technology. 

Advanced Packaging for Chiplet Era: Chiplet architecture, moving from monolithic to multi-tile devices, is becoming a key technology to expand computing resources with integrated functional units on a same package. Chiplet is not only driving the packaging technology including 2.xD/3D integration and high density substrate technology with process and material, but also revolutionizing applications requiring highly advanced computing such as 5G, AI, automotive, edge computing and mobile components. The symposium tries to forecast where the packaging technology is heading. In 2023, our focus is on key electronics packaging technologies pulling by Chiplet architecture on the following main topics: Photonics, Advanced Packaging, Process & Material, Power & Automotive Electronics, Bioelectronics & Healthcare, and Signal/Power Integrity.

The abstract deadline is 29 May, 2023.

Submit abstracts here

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Electronics Packaging Technology Conference (EPTC) is an international event organized by the IEEE RS/EPS/EDS Singapore Chapters and co-sponsored by the IEEE Electronics Packaging Society (EPS). Since its inauguration in 1997, EPTC has been established as a highly reputable international electronics packaging conference and is the IEEE EPS flagship conference in the Asia and Pacific Region. It aims to cover the complete spectrum of electronic packaging technology and it is a major forum for the exchange of knowledge and provides opportunities to network and meet leading experts.

The 25th Electronics Packaging Technology Conference (EPTC 2023) will take place from 5th December to 8th December 2023 in Singapore. It will feature keynotes, technical sessions, invited talks, panels, workshops, exhibitions, and networking activities. Topics include modules, components, materials, equipment technology, assembly, reliability, interconnect design, device and systems packaging, heterogeneous integration, wafer-level packaging, flexible electronics, LED, IoT, 5G, emerging technologies, 2.5D/3D integration technology, smart manufacturing, automation, and AI. This year marks the 25th anniversary of the EPTC history. The organizer will extend the program from a 3-day event to a 4-day event to celebrate this occasion. 

Do not miss this opportunity to be part of EPTC2023! We invite you to submit your abstracts online by the deadline 31 May 2023 through https://www.eptc-ieee.net/

Submission deadline 21 June, 2023

IMPACT 2023 Conference, organized by IEEE-EPS-Taipei, iMAPS-Taiwan, ITRI, and TPCA, is the largest gathering of PCB and packaging professionals in Taiwan. This year's event will be held from Oct. 25th-27th at Taipei Nangang Exhibition Center in conjunction with TPCA Show 2023. The symposium will focus on the theme “IMPACT on the future of HPC, AI, and Metaverse" , exploring the latest electronic technologies and fostering collaboration among enterprises and organizations.


*Scope covers from PACKAGING TO PCB; papers relevant to the below scopes are encouraged to submit but NOT limited to.


P1. Advanced Packaging Technologies

Wafer-level packaging, Panel-level packaging, Flip chip packaging, Chip scale packaging, Fan-in/fan-out technologies, Multi-chip modules, Fine pitch/high pin packaging solution, Heterogeneous integration (side-by-side integration, vertical stacking integration, chiplet, high bandwidth memory), High performance computing package, Si interposer, Organic interposer, Fanout package, Si bridge, Advanced substrate, 3DIC, Hybrid bonding, TSV, Wafer bonding, Mobile heterogeneous integration (SiP, PoP, PiP etc.), and Other new technologies for advanced microelectronics.

P2. Power Electronics Packaging

Si/GaN/SiC based power device and module (IGBT, MOSFET, HEMT, diode, IPM etc.), Power electronic module systems (inverter, converter, rectifier etc.), Fabrication and assembly, Low-temperature bonding, Sintered Ag/Au bonding, Solid-Liquid Interdiffusion (SLID) bonding, Interconnection (wire-bonding, Cu clip bonding, chip embedded PCB etc.), Encapsulant material, Advanced cooling system, Ceramic substrate technologies (DBC, IMS, DPC, AMB etc.), High-performance passive components (super capacitor, inductor etc.), and Other related technologies.

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Call for Papers on Multiphysics Aspects of Power Electronics Packaging - Power Die, Power Module and Converter Level

The IEEE Transactions on Components, Packaging, and Manufacturing Technology (T-CPMT)  is a flagship journal focused on advancing the knowledge and dissemination of research on multiple electronics packaging technologies. T-CPMT is pleased announce a Call for Papers for a Special Section focused on multi-physics aspects of packaging of power electronics at the die/chip, module and converter scales. This can include fundamental research aspects related to emerging high-voltage, high-temperature, high-switching-frequency power electronics, packaging materials, thermal materials and interfaces, fluid-based thermal management technologies, reliability, multi-physics integration at the device, module and converter levels. It could also include the demonstration of the power die and/or the power module and/or the converter in multiple applications cutting across transportation, data centers, radio frequency, directed energy, wind, solar, as well as grid-tied applications. 

Transportation is intended to capture light-, medium- and heavy-duty on-road vehicles, off-highway vehicles for construction, agriculture, mining, aviation, marine, rail, and aerospace. Advancements in topologies, thermal management and reliability in the power die, modules and converters based on silicon, silicon carbide, gallium nitride, other wide-bandgap and ultra-wide-bandgap materials are solicited. Within the converter, in addition to device packaging/power modules, contributions focused on capacitors, magnetics, gate drivers, and circuit boards are also encouraged. Original research, review or perspective articles are all solicited with emphasis on original research.

Authors should select "Special Section on Power Electronics" when submitting their papers and note in their cover letter that the manuscript is being submitted for the Special Section on Power Electronics Packaging. This will ensure that the manuscript is assigned correctly.

Submit Papers here and select "Special Section on Power Electronics"

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Maya Chandrakar1 , Kamal Solanki1 , Manoj Kumar Majumder1 and Rohit Sharma2, 3

1International Institute of Information Technology, Naya Raipur, CG, 493661

2Department of Electrical Engineering, Indian Institute of Technology Ropar, Rupnagar, PB, 140001

3School of Electrical Engineering and Computer Science, Pennsylvania State University, University Park, PA, 16801



Abstract—Chips are converted into reliable electronic devices through the process of electronic packaging throughout the process of electronics fabrication. 3D electronic packaging architectures with heterogeneous integration techniques have witnessed considerable demand as package density and functional diversity have increased. Despite the new architectural possibilities and enhanced performance offered by 3D integration, signal integrity and reliability problems still exist since packaging systems usually exhibit geometric discontinuities due to through silicon vias (TSVs), free edges, and multiple interfaces. Hence, manufacturing of high quality and reliable TSVs was and will remain a major enabler for the adoption of new 3D packaging technologies. TSV faults must be screened promptly during the manufacturing process because they could cause critical challenges during the initial phases of fabrication. Consequently, the mechanical stress and chip-package interaction are addressed as being major threats for 3D TSV IC failures. The emergence of various defects in 3D TSV ICs from fabrication to packaging is outlined and discussed in this article. Also, several defect mechanisms and fault structures causing unstable package performance and impaired device reliability are explained..

I. Introduction

To cater with the growing demand for the miniaturization of electronic devices, the trend in the semiconductor industry is progressively transitioning from two (2D) to three dimensional (3D) packaging constructions for integrated circuits. The research and prototyping of revolutionary 3D electronic packaging are receiving a lot of attention in order to facilitate higher packaging density, functional diversity and provide new opportunities for present and future applications. Compared to earlier packaging methods, the features of through silicon via (TSV) based 3D packaging technology include a small aperture, fine pitch, and a significant aspect ratio [1]. 

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Vineet Pancholi

Global Test Services

Amkor Technology, Inc

Tempe, AZ USA


 Abstract— The aggressive demand for integration results in multiple dies from the same or completely different fabrication technologies and perhaps different chiplet providers being combined within a single package. Each die may contains functional blocks that together form a complete platform when they are combined. Intrinsic use-case operational temperatures of each functional block are different for a variety of reasons. Package architecture, design and layout, along with material types play an important role to minimize thermal congestion.


In recent years there has been a sharp rise in multi-die package designs because die disaggregation results in higher levels of integration. Numerous publications targeting a large variety of applications exist in the public domain [1, 3]. Multidie packages include Artificial Intelligence (AI), central processing unit (CPU), field-programmable gate array (FPGA), memory, analog, radio frequency (RF), input/output (I/O), serializer/deserializer (SERDES), silicon photonics, sensors, etc. OSAT houses are in a unique position in the industry since they experience a wide sampling of customer products. Higher volumes and a higher mix of products result in a unique perspective of key learnings and avoiding missed steps for product packages with multiple die. Furthermore, 2D, 2.5D and 3D package layouts have unique thermal considerations. 

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You can find the most accessed T-CPMT articles on Xplore here