Reliability Concerns in Through Silicon Via based 3D Integration: Fabrication to Packaging

Maya Chandrakar1 , Kamal Solanki1 , Manoj Kumar Majumder1 and Rohit Sharma2, 3

1International Institute of Information Technology, Naya Raipur, CG, 493661

2Department of Electrical Engineering, Indian Institute of Technology Ropar, Rupnagar, PB, 140001

3School of Electrical Engineering and Computer Science, Pennsylvania State University, University Park, PA, 16801



Abstract—Chips are converted into reliable electronic devices through the process of electronic packaging throughout the process of electronics fabrication. 3D electronic packaging architectures with heterogeneous integration techniques have witnessed considerable demand as package density and functional diversity have increased. Despite the new architectural possibilities and enhanced performance offered by 3D integration, signal integrity and reliability problems still exist since packaging systems usually exhibit geometric discontinuities due to through silicon vias (TSVs), free edges, and multiple interfaces. Hence, manufacturing of high quality and reliable TSVs was and will remain a major enabler for the adoption of new 3D packaging technologies. TSV faults must be screened promptly during the manufacturing process because they could cause critical challenges during the initial phases of fabrication. Consequently, the mechanical stress and chip-package interaction are addressed as being major threats for 3D TSV IC failures. The emergence of various defects in 3D TSV ICs from fabrication to packaging is outlined and discussed in this article. Also, several defect mechanisms and fault structures causing unstable package performance and impaired device reliability are explained..

I. Introduction

To cater with the growing demand for the miniaturization of electronic devices, the trend in the semiconductor industry is progressively transitioning from two (2D) to three dimensional (3D) packaging constructions for integrated circuits. The research and prototyping of revolutionary 3D electronic packaging are receiving a lot of attention in order to facilitate higher packaging density, functional diversity and provide new opportunities for present and future applications. Compared to earlier packaging methods, the features of through silicon via (TSV) based 3D packaging technology include a small aperture, fine pitch, and a significant aspect ratio [1]. 

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