Impact of Thermal Congestion on Advanced Package Test

Vineet Pancholi

Global Test Services

Amkor Technology, Inc

Tempe, AZ USA

 Abstract— The aggressive demand for integration results in multiple dies from the same or completely different fabrication technologies and perhaps different chiplet providers being combined within a single package. Each die may contains functional blocks that together form a complete platform when they are combined. Intrinsic use-case operational temperatures of each functional block are different for a variety of reasons. Package architecture, design and layout, along with material types play an important role to minimize thermal congestion.


In recent years there has been a sharp rise in multi-die package designs because die disaggregation results in higher levels of integration. Numerous publications targeting a large variety of applications exist in the public domain [1, 3]. Multidie packages include Artificial Intelligence (AI), central processing unit (CPU), field-programmable gate array (FPGA), memory, analog, radio frequency (RF), input/output (I/O), serializer/deserializer (SERDES), silicon photonics, sensors, etc. OSAT houses are in a unique position in the industry since they experience a wide sampling of customer products. Higher volumes and a higher mix of products result in a unique perspective of key learnings and avoiding missed steps for product packages with multiple die. Furthermore, 2D, 2.5D and 3D package layouts have unique thermal considerations. 

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