Presenter: Darvin Edwards
Date: November 29, 2018
Time: 11:00 AM EST
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Abstract: Through Silicon Via (TSV) and Fan Out Wafer Level Packages (FOWLP) are two of the most rapidly growing package technologies in today’s semiconductor industry. These package technologies borrow from past packaging processes with many novel additional improvements and refinements to meet the new application needs. New or refined wafer fab and package processes include deep TSV drilling, TSV plating, wafer thinning, backside interconnect fabrication, thermo-compression Cu pillar bonding, capillary and molded underfilling, over molding, temporary carrier attach, and thin die pick-and-place among many others. As with any new package technology, reliability risks must be evaluated with special emphasis on failure mechanisms that might arise from the new package configurations and applications. The package design and process development engineer must understand the factors that play into new technology reliability failure mechanisms, as well as mitigations that can be employed to ensure that highly reliable products can be produced. Without this knowledge, reliability failures are bound to occur.