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Avram Bar Cohen

Professor Avram Bar-Cohen

(1946 - 2020)

On October 10, 2020, we learned sadly, of Prof. Avram Bar-Cohen’s passing.  It is no understatement to call Prof. Bar-Cohen, better known to so many of us simply as Avi, a legend in our field of micro-electronics packaging, especially in the area of thermal management.  His immense body of work, the success of his students, and the positive imprint of his personality and influence is writ large on our community.  His passing leaves behind a very large void in the lives of so many he came in touch with.  

Avi began his university career at the Ben Gurion University (Beer Sheva, Israel), in 1972 after receiving his Ph.D., from the Massachusetts Institute of Technology in 1971 under the guidance of Prof. Art Bergles.  He then moved to the University of Minnesota, followed by a stint as the Chair of the Mechanical Engineering Department, in the A. James Clark School of Engineering, University of Maryland during 2001 to 2010.  Since 2010, he had been on a leave of absence for six years as a Program Manager at DARPA and then as a Principal Engineering Fellow at Raytheon Technologies in the Space and Airborne Systems.  Interspersed with his university career were many years in the industry as he started and ended his professional life at Raytheon; and he spent 5 consequential years at Control Data Corporation during the second half of 1980s.

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Title: Powering Heterogeneous Integration: An overview of the Integrated Power Electronics Chapter of the HIR Roadmap

Date: November 20, 2020

Time: 11:00 AM ET

Presenter: Prof. Patrick McCluskey  

Register Here

Abstract

Heterogeneous integration (HI) is not possible without a source of power for the multiple devices and components involved.  While it is possible to supply this power externally to one or more devices, it is typically advantageous to integrate the conversion and distribution of this power into the HI system. This makes power delivery one of the most critical elements in an HI system and one clearly requiring its own section of the roadmap. 

HI provides significant advantages for power electronics as it permits wide bandgap power devices, which surpass silicon in power handling capability, efficiency, and operating temperature, to be integrated with silicon control, logic, and memory devices and with lower operating temperature passive devices.  Nevertheless, HI of power electronics comes with a raft of challenges for SiP designers, as the power electronics require space, generate heat, and can cause electrical noise in the circuits.

This roadmap for Power Electronics for Heterogeneous Integration addresses the timeline for the development of the power conversion and distribution techniques needed to supply clean, efficient power at a variety of voltages to the wide range of devices in an HI system without significantly increasing system size. The 2019 version of the roadmap focuses on the first of these categories – reducing power converter size.  This requires the development of wide bandgap semiconductor devices which can convert higher levels of power more efficiently, combined with packaging technologies (i.e., interconnection and thermal management) and passive devices that can reduce the size and increase the power density of the converter circuits.  Developing smaller converters is important because utilizing distributed conversion where each component is near to its power supply is critical to minimize interconnection losses and signal noise.

 

Download HIR Chapter 10 Integrated Power Electronics

eptc 2020

Dear Electronics Packaging Colleagues,

First and foremost, I hope that everyone is coping well despite the disruptions caused by the pandemic. We are all affected in one way or another, and it is more important than ever to support each other. We also quickly learned that digital transformation, which all of us have a key role to play, becomes more essential than before. Understanding what is at stake and to ensure continuity, the EPTC 2020 organising committee have decided to carry on with the cause.

The 22nd Electronics Packaging Technology Conference (EPTC 2020) is an international event organized by the IEEE RS/EPS/EDS Singapore Chapter and sponsored by IEEE Electronics Packaging Society (EPS). Since its inauguration in 1997, EPTC has developed into a highly reputed electronics packaging conference in the Asia-Pacific and is well attended by experts in all aspects of packaging technology from all over the world. EPTC is now the flagship conference of IEEE EPS in Region 10.

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The EPS Awards Program recognizes contributions to the profession, industry and the Society through a comprehensive set of awards and recognitions.

EPS Major Awards

A series of EPS Major Awards, recognizing technical contributions and service, is administered by the EPS Awards Committee:

·       Outstanding Sustained Technical Contribution Award

·       Electronics Manufacturing Technology Award

·       David Feldman Outstanding Contribution Award

·       Exceptional Technical Achievement Award

·       Outstanding Young Engineer Award

·       Regional Contributions Award

 

 Nomination Period September 15, 2020- January 25, 2021

Description/Objective:

To promote, recognize, and support PhD level study and research within the Electronics Packaging Society’s field of interest.

Prize: 

A plaque and a single annual award of US$5,000, applicable towards the student’s research.

Eligibility:

Candidate must be an IEEE EPS member, at the time of nomination, and be pursuing a doctorate degree within the EPS field of interest on a full-time basis from an accredited graduate school or institution.The candidate must have studied with her/his advisor for at least 1 year, at the time of nomination, to be eligible. A Student who received a Fellowship award from another IEEE Society, within the same year, or is a previous EPS Fellowship winner is ineligible.

Nomination Period September 15, 2020 - January 25, 2021

Nomination Form

The growth of data center computing power and the increase in the amount of data being transmitted within and between systems is driving interesting and innovative ways to design electronic systems. Building the systems with robust, predictable, and energy-efficient electrical performance is essential to designing and manufacturing complex systems that scale with the exponential increase in computing and networking operations.

A core interest of members of the IEEE EPS technical committee on EDMS (electrical design, modeling, and simulation) is developing the technology needed to produce these systems. Within EDMS, there are several activities that address the challenges being faced. This article gives an overview of the scope of activities and how EDMS plays a part in supporting the members and the broader community in their efforts.

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By Dr. Willem van Driel, Signify, willem.van.driel@signify.com

Reliability is an essential scientific and technological domain intrinsically linked with system integration. Nowadays, semiconductor industries are confronted with ever-increasing design complexity, dramatically decreasing design margins, increasing chances for and consequences of failures, shortening of product development and qualification time, and increasing difficulties to meet quality, robustness and reliability requirements. The scientific successes of many micro/nano-related technology developments cannot lead to business success without innovation and breakthroughs in the way that we address reliability through the whole value chain.

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Chair: Bing Dang

Status

In the past decades, the driving force for Advanced Packaging has shifted from the traditional PC and server products to 5G mobile devices, IoT devices, wearable devices, automotive electronics as well as medical devices. Great challenges and tremendous opportunities are present in the field of materials and processing. For instance, today’s new car requires as many  as 8,000 active semiconductors in up to 100 interconnected control units. Another example is the miniaturization of  consumer electronics such as smart wearables. Smaller chip package and lower cost call for novel package processes such as FO-WLP and FO-PLP. Higher quality and better performance are required for novel interconnection, dielectric, adhesive, thermal interface materials, as well as substrate materials, etc. The mission of M & P TC is to keep close track of industry trending, build a community for more collaboration, develop insightful guidance for the broad audience in EPS.

Impact routes

Establish monthly or bi-monthly committee meetings

Publish Newsletters on our website

Promote the awareness using social media such as Linkedin

Organize webinars in areas of interest

Chair: Dereje Agonafer 

Website: under construction: https://cmte.ieee.org/eps-tmm/

The Thermal Management and Thermomechanical Design Technical Committee is concerned with all aspects of thermal, thermo-mechanical, electro-thermal phenomena related to electronic/microelectronics packaging and electrical systems. The subjects of interest include:

  • Electronic Cooling and Thermal Management of Component and System
  • Thermal Design and Analysis
  • Coupled Electro-Thermal Phenomena
  • Thermal and Thermomechanical Measurements
  • Thermal Mismatches and Stressses
  • Temperature Induced Fracture and Moisture Stresses in IC Package
  • Thermomechanical Design and Analysis of Component and System
  • Thermomechanical Computer Aided Design and Engineering
  • Co-Design
  • Heterogeneous Integration

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Reliability Component Stress Analysis and Derating Specification that establishes uniform methods to increase electronic, electrical, or electromechanical product reliability by decreasing the amount of applied stress (i.e., voltage, current, temperature, power, etc.) to components within the system. They're holding their kick-off meeting 17 November.

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