NEW: The IEEE Transactions on Components, Packaging and Manufacturing Technology will now include a Letters section within the publication. Papers will be a maximum of 4 pages and relate to the research and application on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment. The intent of the Letters section is to enable the rapid dissemination of the latest information in topics of interest to the readership of the IEEE Transactions on Components, Packaging and Manufacturing Technology and thus improve dialog across the community.
The technical content of papers must be both new and signiﬁcant.
The standard length for an accepted manuscript must not exceed 4 pages. in order to accommodate a comprehensive reference list of pre-published and to-be-published articles with full authors’ names, title, and (where available).
When submitting your Letters into ScholarOne, select "Letters" as paper type.
The EPS Awards Program recognizes contributions to the profession, industry and the Society through a comprehensive set of awards and recognitions.
Presenter: Darvin Edwards
Date: November 29, 2018
Time: 11:00 AM EST
Earn 1 Professional Development Hour (PDH) for completing the webinar - Complete Form
Abstract: Through Silicon Via (TSV) and Fan Out Wafer Level Packages (FOWLP) are two of the most rapidly growing package technologies in today’s semiconductor industry. These package technologies borrow from past packaging processes with many novel additional improvements and refinements to meet the new application needs. New or refined wafer fab and package processes include deep TSV drilling, TSV plating, wafer thinning, backside interconnect fabrication, thermo-compression Cu pillar bonding, capillary and molded underfilling, over molding, temporary carrier attach, and thin die pick-and-place among many others. As with any new package technology, reliability risks must be evaluated with special emphasis on failure mechanisms that might arise from the new package configurations and applications. The package design and process development engineer must understand the factors that play into new technology reliability failure mechanisms, as well as mitigations that can be employed to ensure that highly reliable products can be produced. Without this knowledge, reliability failures are bound to occur.
This webinar will briefly review current predominant fabrication processes for both TSVs and FOWLPs. Major TSV reliability risks such as Cu pumping, side wall dielectric cracking, Back-End-of-Line (BEOL) cracking, underfill voids, wafer backside contamination, and thermal issues will be addressed with multiple solutions provided. The FOWLP discussion will highlight chip first vs. chip last issues such as chip shifting and warpage and will draw comparisons between FOWLP board level thermal cycling and drop reliability vs. FCBGAs and WLCSPs. Example finite element modeling and experimental studies will be presented to illustrate the steps that must be taken to insure reliability has been designed in as the package processes are being developed.
Bio: Mr. Darvin Edwards has 38 years of experience in the IC packaging industry. He is currently owner of Edwards’ Enterprise Consulting LLC which specializes in helping companies solve package reliability problems, assisting in rapid product development, as well as providing worldwide training on topics such as package reliability, materials, TSV and FOWLP technologies, package design and surface mount techniques. Previously, he worked 14 years as a Fellow at Texas Instruments, managing the Dallas electrical, thermal and thermomechanical modeling team responsible for chip-package interactions and reliability of multiple TI product lines. He has served the IEEE EPS as Member at Large and is the co-chair of the Electronics Components and Technology Conference Applied Reliability committee. Mr. Edwards has authored and co-authored over 65 papers and articles in the field of IC packaging, has written two book chapters, and holds 24 US patents. He is an IEEE Senior Member.
Right now, blockchain is helping reshape industries in domains as varied as finance, healthcare, energy, supply chain and Internet of Things (IoT). As the technology continues to evolve, engineers moving into management roles are expected to be up to speed with market developments.
Given the demand from engineers for professional development that helps smooth their upward career path, IEEE is offering a live, virtual event–Advanced Blockchain for Enterprise–on 4 December 2018 - 5 December 2018 12:00PM-1:00PM ET daily.
Over the course of these two 1-hour sessions, attendees will gain a deeper understanding of recent enterprise-level innovations powered by blockchain plus much more:
● Discover key differences between permissioned blockchain for business and public applications like Bitcoin
● Learn which government policies and regulations will have a significant influence over blockchain’s global growth
● Hear how businesses and industries can collaborate to reinvent themselves in the age of blockchain
REGISTER HERE to receive the EPS partner discount or use code 18ABEPS at checkout.
Upon successful completion of the post-event assessment, attendees will earn a digital certificate from IEEE along with 0.2 Continuing Education Credits (CEUs) / 2 Professional Development Hours (PDHs).
Advanced Blockchain for Enterprise will be presented by corporate blockchain strategist and MIT lecturer, Steve Derezinski. Steve Derezinski consults with major corporations on blockchain strategy and new blockchain ventures. He taught Blockchain Ventures at MIT Media Lab and Babson College, and sits on a number of boards and funding panels. He is an expert reviewer for a Federal Agency’s Blockchain Funding and a subject matter expert for large philanthropic foundations in the USA and EU. He holds a BS from MIT and MBA from MIT Sloan.
Fan-out wafer-level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 10 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wire bond and bump interconnections, substrates, leadframes, and the traditional flip-chip or wire bond chip attach and underfill assembly technologies across multiple applications. The next step is economy of scale: the conversion from 300mm to panel Panel Fan-Out. This topic was discussed at IEEE Electronics Package Society’s Electronic System-Integration Technology Conference (ESTC) conference in Dresden, Germany, on September 19, 2018. In a panel called “ESTC called “Fan-Out Panel: Is the Industry Ready?” panelists Jan Vardaman of TechSearch International, Tanja Braun, Ph.D., of Fraunhofer IZM, Marion Weigand of HDMicrosystems, and Jan Kellar of Deca Technologies and chaired by Beth Keser, Ph.D., of Intel Corporation, discussed how their company or consortium is addressing (or not addressing) the panel fan-out market and discussedthe intersection with European markets such as automotive, IoT, and flexible electronics. Not coincidentally, this was an all-female technical panel, the first of its kind in the electronic packaging industry.
L to R: Marion Weigand, Tanja Braun Ph.D., Jan Vardaman, Jan Kellar, and Beth Keser, Ph.D. at ESTC 2018, Dresden, Germany.
The HIR workshop was held on Sept 19 afternoon and was part of the 2018 GE / BU Electronics Packaging Symposium. The attendees for the workshop were a mix of academics and industry, with many from Binghamton University, IBM, GE, Lockheed Martin and BAE Systems. The keynote for the workshop was given by Rozalia Beica from Dow, this was followed by presentations from the following Technical Working Groups: 2.5D / 3D Packaging, Medical / Health / Wearable, Single / Multi Chip Packages, Aerospace / Defense, Thermal, Wafer Level Fan-Out and High Performance Computing.
EMPC in Pisa offers the best of microelectronics packaging and interconnection technologies, providing top quality coverage of technological innovation in this field. The four days will compromise Tutorials/Short Courses and the Conference and Exhibition during 16th to 19th September at Palazzo Dei Congressi, an ideal venue which includes excellent lecture auditoria, exhibition space and a great social venue.
2018 15th China International Forum on Solid State Lighting: International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS)
Oct 23, 2018 - Oct 25, 2018
San Jose, CA USA
Oct 23, 2018 - Oct 25, 2018
2018 13th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)
Oct 24, 2018 - Oct 26, 2018
The next EPS Board of Governors (BoG) meeting will be held December 8, 2018 in conjunction with EPTC in Singapore.
All Members are welcome to attend. The Board members will be discussing, among other things, the strategic direction of the Society as well as the latest projects and events the Society is working on. An Informational session will be held Friday evening, December 7, 2018.
Date: Saturday Decembere 8, 2018
Time: 8:00 AM - 5:00 PM
Location: Resorts World Sentosa, Singapore