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The 2019 Heterogeneous Integration Roadmap (HIR) is a roadmap to the future of electronics identifying technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration among industry, academia and government to accelerate progress.

The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of emerging devices and materials with longer research-and-development timelines.

View and Download the 2019 HIR

Press Release

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The Heterogeneous Integration Roadmap (HIR) held a Workshop at IMAPS International Symposium on Microelectronics in Boston, MA, the largest IMAPS annual conference. The HIR workshop was very well attended with standing room only at the back of the conference room. The workshop session chaired by Urmi Ray (consultant) & V. Mathew (NXP), includes HIR roadmap overview, followed by presentations from four Technical Working Groups.    

 

Heterogeneous Integration Roadmap Overview        William Chen (ASE)
SiP & Module                                                              Andreas Grassmann (Infinion)
High Performance Computing & Data Center            Dale Becker (IBM)
Mobile                                                                         Benson Chan (Binghamton University)
Wafer Level Packaging (WLP) Fan-in & Fan-out       John Hunt (ASE)

 

The next HIR Workshops will be held at IMPACT in Taiwan (October 23 – 25) and EPTC in Singapore (December 4-6).

We look forward to seeing you at one of the upcoming HIR workshops.

 

IMAPS

The EPS Awards Program recognizes contributions to the profession, industry and the Society through a comprehensive set of awards and recognitions.

EPS Major Awards

A series of EPS Major Awards, recognizing technical contributions and service, is administered by the EPS Awards Committee:

 Nomination Period September 15, 2019 - January 21, 2020

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Description/Objective:

To promote, recognize, and support PhD level study and research within the Electronics Packaging Society’s field of interest.

Prize: 

A plaque and a single annual award of US$5,000, applicable towards the student’s research.

Eligibility:

Candidate must be an IEEE EPS member, at the time of nomination, and be pursuing a doctorate degree within the EPS field of interest on a full-time basis from an accredited graduate school or institution.The candidate must have studied with her/his advisor for at least 1 year, at the time of nomination, to be eligible. A Student who received a Fellowship award from another IEEE Society, within the same year, or is a previous EPS Fellowship winner is ineligible.

Nomination Period September 15, 2019 - January 21, 2020

Nomination Form

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We invite you to be among the first to have your article peer-reviewed and published in the new Electronics Packaging section within IEEE Access. This is an exciting opportunity for your research to benefit from the high visibility of IEEE Access.  Your work will also be exposed to 5 million unique monthly users of the IEEE Xplore® Digital Library.

The Electronics Packaging Section within IEEE Access will draw on the expert technical community to continue IEEE’s commitment to publishing the most highly-cited content. The Journal peer-review process targets a publication period of 6 weeks for most acceptecd papers. This journal is fully open and compliant with funder mandates, including Plan S.

Scope

The IEEE Electronics Packaging Society section in IEEE Access covers the scientific, engineering, and production aspects of materials, components, modules, hybrids and micro-electronic systems for all electronic applications, which includes technology, selection, modeling/simulation, characterization, assembly, interconnection, packaging, handling, thermal management, reliability, testing/control of the above as applied in design and manufacturing. Examples include optoelectronics and bioelectronic systems packaging, and adaptation for operation in severe/harsh environments. Emphasis is on research, analysis, development, application and manufacturing technology that advance state-of-the-art within this scope.

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Most Popular Articles according to Xplore® usage statistics

3-D Printed Metal-Pipe Rectangular Waveguides

Mario D’Auria ; William J. Otter ; Jonathan Hazell ; Brendan T. W. Gillatt ; Callum Long-Collins ; Nick M. Ridler ; Stepan Lucyszyn

Publication Year: 2015, Page(s):1339 - 1349 


A Low-Cost and High-Gain 60-GHz Differential Phased Array Antenna in PCB Process

Tao Zhang ; Lianming Li ; Haiyang Xia ; Xujun Ma ; Tie Jun Cui

Publication Year: 2018, Page(s):1281 – 1291


Inkjet Printing of Wideband Stacked Microstrip Patch Array Antenna on Ultrathin Flexible Substrates

Wen Tao Li ; Yong Qiang Hei ; Peter Mack Grubb ; Xiao-Wei Shi ;Ray T. Chen

Publication Year: 2018, Page(s):1695 – 1701

A Filtering Dual-Polarized Antenna Subarray Targeting for Base Stations in Millimeter-Wave 5G Wireless Communications

Hui Chu ; Yong-Xin Guo

Publication Year: 2017, Page(s):964 – 973


Fan-Out Wafer-Level Packaging for Heterogeneous Integration

John H. Lau ; Ming Li ; Margie Li Qingqian ; Tony Chen ; Iris Xu ;Qing Xiang Yong ; Zhong Cheng ; Nelson Fan ; Eric Kuah ; Zhang Li ; Kim Hwee Tan ; Yiu-Ming Cheung ; Eric Ng ; Penny Lo ; Wu Kai ; Ji Hao ; Koh Sau Wee ; Jiang Ran ; Cao Xi ; Rozalia Beica ;Sze Pei Lim ; N. C. Lee ; Cheng-Ta Ko ; Henry Yang ; Yu-Hua Chen ; Mian Tao ; Jeffery Lo ; Ricky S. W. Lee

 

Publication Year: 2018, Page(s):1544 – 1560

 

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The 2019 Semiconductor Advanced Packaging Workshop organized by IEEE EPS Malaysia Chapter is back! The bi-annual one-day technical workshop took place at Eastin Hotel, Penang and New World Hotel, Petaling Jaya scheduled on September 24th and 25th respectively. It featured contemporary packaging trends and development of emerging technologies from two distinguished speakers in the field of semiconductor: (1) Prof. Dr. Madhavan Swaminathan (Georgia Tech, USA) on “Intelligent Digital Convergence for AI and 5G” (2) Dr. John Lau Hon Shing (UMTC, Taiwan) on “Fan-Out Wafer/Panel-Level Packaging & Heterogeneous Integrations (SiPs)”.

 

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The 2020 IEEE 6th World Forum on Internet of Things (WF-IoT 2020) is the premier conference of the IEEE IoT Initiative. Every year the conference is attended by hundreds of most active participants from research community, government and public sector,  small business, multinational corporations and industry. The technical papers, presentations and events at this conference are focused on contributions to enhance and accelerate the adoption of IoT technologies and applications for the benefit of humanity. WF-IoT 2020 will include a multi-dimensional program of technical research papers, expert presentations, panels, workshops, tutorials and industry forum on the latest technology developments and innovations in many fields and disciplines that drive the utility and vitality of IoT solutions and applications.

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