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Election of EPS Members at Large continues through October 19, 2021.

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Election Principles 

The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members at Large will be selected each year to represent the regional composition of the Society membership and one Member at Large will be selected to represent the Young Professional community. A Young Professional is an individual that has completed their first academic degree within the last 15 years.

Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG.  The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect members-at-large from within their Region only (that is, members in Region 8 vote for Members-at-Large from Region 8, members in Region 10 vote for Members-at-Large from Region 10; etc.). There is no election of a Young Professional this year.

The EPS Awards Program recognizes contributions to the profession, industry and the Society through a comprehensive set of awards and recognitions.

EPS Major Awards

A series of EPS Major Awards, recognizing technical contributions and service, is administered by the EPS Awards Committee:

·       Outstanding Sustained Technical Contribution Award

·       Electronics Manufacturing Technology Award

·       David Feldman Outstanding Contribution Award

·       Exceptional Technical Achievement Award

·       Outstanding Young Engineer Award

·       Regional Contributions Award

 

The Society also sponsors a PhD Fellowship to promote, recognize, and support PhD level study and research within the Electronics Packaging Society’s field of interest.

Awards Nomination Form

PhD Fellowship Nominiation Form 

Nomination Period September 8, 2021 - January 26, 2022

E. Jan Vardaman, President and Founder, TechSearch International, Inc. 

Unexpected demand, global supply chain uncertainty, accidents, and weather-related events have resulted in semiconductor shortages.  All types of substrates are in short supply; including substrates for chip scale packages (CSPs) and flip chip ball grid arrays (FC-BGAs).  Despite some capacity expansion over the next few years, and new plants planned to come online in 2024-25, the situation is not expected to improve for at least two to three years.  Some companies are considering substitutes that do not use substrates, including fan-out wafer level packages (FO-WLPs).  Layer count reduction in substrate designs with the adoption of RDL is also under consideration.

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In September 2021, the first IEEE Electronic Packaging Society Student Branch Chapter was established at Addis Ababa Institute of Technology, Addis Ababa University in Addis Ababa, Ethiopia. The IEEE EPS Santa Clara Chapter (Chair: Annette Teng) from Northern California played a critical role by being a big brother and providing the financial support to start the student branch and chapter 3000 miles away. We would also like to thank Dr. Fetene Mulugeta, from the School of Electrical and Computer Engineering, for serving as the faculty advisor of the "IEEE Addis Ababa University Student Branch Chapter.” This and similar student branches will play key roles in IEEE EPS conferences to be held on the continent of Africa. The first workshop is to be held in Addis Ababa early next year (www.dtmes.org).

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During the 25th – 30th of October 2021, a unique "International Electronics Week in Central and South-Eastern Europe" will be organized for the second time as an online event. This live scientific event coalesces three main events held traditionally in Romania: TIE, TIEPlus (www.tie.ro), and SIITME (www.siitme.ro).

The 6th edition of the TIEPlus contest, on Monday the 25th of October, is the final stage in the industrial certification of the students' knowledge in signal and power integrity and virtual prototyping. The event is followed by a scientific workshop debating various topics, such as electrical, mechanical, and thermal issues of multi-layer chip capacitors.

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Symposium on Reliability for Electronics and Photonics Packaging (IEEE- REPP: Register NOW 

As the organizing team, we are excited to invite you to register for the EPS second symposium of REPP. It features eminent Plenary talks , invited talks and presentations in the evolving and exciting field of Electronics and Photonics packaging and the program details can be reviewed through this link.

This 2-day virtual event will focus on quantified reliability, accelerated testing and probabilistic assessments of the useful lifetime of electronic and photonic assemblies, packages and systems. This includes failure modes, mechanisms, design, simulation and accelerated testing.

   

Kindly sign up for our Dlist herefor continuing updates. 

 

Dates:  Nov. 11-12th, 2021

 

Location: Online event, links to the event will be sent after registration.

 

From The Organizing Committee

Celebrating IEEE Day, Special offer on continuing education courses, upcoming virtual events, and more!

IEEE Education week graphic

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The Electronics System-Integration Technology Conference (ESTC) is the premier international event in the field of electronics packaging and system integration. The conference is organized every two years in Europe and is supported by IEEE-EPS in association with IMAPS-Europe. The 9th ESTC will be taking place in Sibiu, Romania. Placed in the middle of Romania, surrounded by the the high Carpathian Mountains and Cibin river, Sibiu is a citadel of the European electronics industry and represents a place where culture, landscape, gastronomy and profession merge in a friendly pleasant environment.

The ESTC 2022 seeks original, noncommercial papers describing research and innovations in all areas of electronics packaging and system integration. Authors are invited to submit an abstract describing recent work. Abstracts must detail the objectives of the work presented and demonstrate new results.

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Knowing a system’s reliability is knowing the key to success.

The developers of modern electronic components and systems are facing a double challenge: Meeting ever more stringent requirements in ever faster-paced development cycles. In this situation, understanding their systems’ reliability becomes a crucial factor.

Join our two-day seminar

After a successful round last year, Fraunhofer IZM is again offering a two-day seminar that provides you with expert-level methods and background knowledge for ensuring reliability in your processes for the development and production of electronic systems.

Seminar agenda
Covering the topic in its entirety

• Definitions and an introduction to the important terms
• Methods for system assessments
• Stress impacts and resulting failure mechanisms
• The empirical data and physics used in failure modelling
• Systematics of FE simulation
• Implementing realistic stress tests
• Analysing and interpreting test results
• Handling reliability characteristics/ parameters
• Assuring reliability by condition monitoring
• Analytical measurement methods



 

 




The programme has been carefully curated to cover the reliability of electronic systems in all development phases.

The seminar will be held via MS Teams.

Seminar fees:
 850 € for two days.
The seminar is exclusively limited to 30 participants.



 

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Title: Fan Out Packaging and its Diversity

Date: Tuesday, November 30, 2021

Time: 4:30 PM (UTC+01:00) Brussels, Copenhagen, Madrid, Paris

Presenter: John Hunt - Senior Director, Engineering Marketing & Technical Promotion ASE (US) Inc.

Abstract: Fan Out technology has evolved in recent years as an alternative package answering a growing need for miniaturization in electronics, while also providing improved electrical interconnectivity for more advanced multi-die solutions. This has been accomplished through the integration of a wide variety of wafer and panel level technologies, processes and materials. Fan out has enabled both the miniaturization of low-end packages for mobile applications, as well as the interconnection required for more advanced complex package assemblies. We will review these Fan Out technologies, including Wafer Level Fanout, Panel Level Fanout, and multiple combinations of chip first and chip last solutions. The resulting packaging combinations that evolve from these technologies will only be limited by our imaginations, and our creativity in innovating them.

To register: send an email to jean-charles.souriau@cea.fr

Open to Everyone!

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