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Title: New Results on Electromigration Modeling - A departure from Blech's Theory

Date: September 25, 2019

Time: 11:00 AM EDT

Presenter: Xuejun Fan

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We have recently developed a multi-physics-based general coupling theory for electromigration (J. Appl. Phys. 125, 105101, 2019). The results show the mechanical stress is significantly less than the existing literature solutions. In addition, the vacancy concentration gradient plays an important role in formulating electromigration problems. We revisited Blech’s theory and a new threshold criterion for electromigration failure has been developed. This is a major departure from the Blech’s theory, and the preliminary results show the predicted results are consistent with the Blech’s original test data.

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The EPS Board of Governors (BoG) includes 18 Members-at-Large, elected by the full voting membership of the Society. The three-year terms of the Members-at-Large are staggered -- so that six Members-at-Large to the Board of Governors are elected annually.

Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG.  The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large plus continuing Members-at-Large has the proper proportion of representatives from each Region/grouping of Regions.

Each Region/grouping of Regions will have a separate slate of candidates from that Region.  Voting members will elect members-at-large from within their Region only (that is, members in Region 8 vote for Members-at-Large from Region 8, members in Region 10 vote for Members-at-Large from Region 10; etc.).

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We invite you to be among the first to have your article peer-reviewed and published in the new Electronics Packaging section within IEEE Access. This is an exciting opportunity for your research to benefit from the high visibility of IEEE Access. Your work will also be exposed to 5 million unique monthly users of the IEEE Xplore® Digital Library.

The Electronics Packaging Section within IEEE Access will draw on the expert technical community to continue IEEE’s commitment to publishing the most highly-cited content. Our goal is to publish quickly - the rapid peer review process has demonstrated an average submission to publication time of 5.0 weeks for the first 6 months of 2019.  This journal is fully open and compliant with funder mandates, including Plan S.


The IEEE Electronics Packaging Society section in IEEE Access covers the scientific, engineering, and production aspects of materials, components, modules, hybrids and micro-electronic systems for all electronic applications, which includes technology, selection, modeling/simulation, characterization, assembly, interconnection, packaging, handling, thermal management, reliability, testing/control of the above as applied in design and manufacturing. Examples include optoelectronics and bioelectronic systems packaging, and adaptation for operation in severe/harsh environments. Emphasis is on research, analysis, development, application and manufacturing technology that advance state-of-the-art within this scope.

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Join us at the Heterogeneous Integration Roadmap (HIR) Workshop hosted by the 2019 ASME InterPACK Conference

Our Industry has reinvented itself through multiple disruptive changes in technologies, products and markets. With the rapid migration of logic, memory and applications to the Cloud infrastructures, Data Centers and 5G Networks, the Internet of Things (IoT) to internet of everything (IOE), Autonomous Vehicles, the proliferation of Smart Devices every where, and increasing interest in artificial intelligence (AI) & Virtual Reality (VR), the pace of innovation is increasing to meet these challenges. What are the paths forward?

There is no cost to attend the HIR workshop only. Click on the blue registration button and pick the HIR workshop only option.

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The UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS) would like to provide you with an opportunity to present a poster about your research and network with our attendees at the 2019 UCLA CHIPS Workshop.  The workshop will take place on Wednesday, November 6, 2019 at UCLA. Details regarding the poster submission are below.

Research topics of interest

  • Heterogeneous integration on rigid substrates
  • Heterogeneous integration on flexible substrates
  • Neuromorphic circuits and systems
  • Devices that support non von Neumann architectures
  • Advances in packaging and interconnects
  • Packaging reliability

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