The EPS Board of Governors (BoG) includes 19 Members-at-Large, elected by the full voting membership of the Society. Six Members at Large will be selected each year to represent the regional composition of the Society membership and one Member at Large will be selected to represent the Young Professional community. A Young Professional is an individual that has completed their first academic degree within the last 15 years.
Regional Members-at-Large are elected to achieve totals proportionate to the geographic distribution of EPS members. Any IEEE Region/grouping of Regions determined to have at least 10% of total EPS members will have the proportional number of Member-at-Large positions designated to it for representation on the BoG. The slate of candidates for each year’s election will be constructed to ensure that the resulting total of newly elected Members-at-Large and continuing Members-at-Large, respectively, has the proper proportion of representatives from each Region/grouping of Regions. Each Region/grouping of Regions will have a separate slate of candidates from that Region. Voting members will elect members-at-large from within their Region only (that is, members in Region 8 vote for Members-at-Large from Region 8, members in Region 10 vote for Members-at-Large from Region 10; etc.).
The Young Professional Member at Large will be elected by all eligible voting members of the Society from a slate that is finalized by the Nominations Committee.
The EPS Awards Program recognizes contributions to the profession, industry and the Society through a comprehensive set of awards and recognitions.
EPS Major Awards
A series of EPS Major Awards, recognizing technical contributions and service, is administered by the EPS Awards Committee:
The Society also sponsors a PhD Fellowship to promote, recognize, and support PhD level study and research within the Electronics Packaging Society’s field of interest.
Nomination Period September 15, 2020- January 25, 2021
In response to the COVID-19 situation, ESTC 2020 has moved to a 100% virtual platform, and the conference will be carried out live! The live format will allow interaction similar to an in-person conference. The digital format will give new possibilities, such as recording of presentations allowing to catch up presentations in parallel sessions. Heterogeneous Integration Roadmap (HIR) workshop, hosted by ESTC, will be held September 15, 9:00 am – 11:50 am Central European Summer Time. The HIR workshop will be open to the general public and is free.
We invite you to register now for ESTC: https://www.estc-conference.net/estc-2020/registration-1
Access to the HIR Workshop will be free of charge, and available through a Zoom weblink at https://www.estc-conference.net/estc-2020/hir-workshop
Attendees are advised to download the Zoom client (free of charge) prior to the HIR workshop: https://zoom.us/support/download .
Submit an abstract for the 71st IEEE Electronic Components and Technology Conference (ECTC), to be held June 1 - June 4, 2021, at Sheraton San Diego Hotel & Marina, San Diego, CA. This premier international conference, sponsored by the IEEE Electronics Packaging Society (IEEE EPS), covers a wide spectrum of electronic packaging technology topics, including components, materials, assembly, interconnect design, device and system packaging, wafer level packaging, Si photonics, LED and IoT, optoelectronics, 2.5D and 3D integration technology, and reliability.
Deadline October 4, 2020.
Prof. CQ Cui
Chairman, Technical program
Guangdong University of Technology
The 21st International Conference on Electronics Packaging Technology (ICEPT 2020) was held at the Conference Center of Guangzhou Science City from August 12th to 15th, 2020. The conference was hosted by Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangdong University of Technology (GDUT), IEEE Electronics Packaging Society, Electronic Manufacturing and Packaging Technology Society of the Chinese Institute of Electronics, organized by School of Electromechanical Engineering, Guangdong University of Technology / State Key Laboratory of Precision Electronic Manufacturing Technology and Equipment, and co-organized by National Center for Advanced Packaging (NCAP), State Key Laboratory of Mobile Network and Mobile Multimedia Technology (ZTE), Hong Kong Applied Science and Technology Research Institute Co. Ltd., Guangdong Fozhixin Microelectronics Technology Research Co., Ltd., Guangdong XH Microelectronics Co., Ltd., Guangzhou Semiconductor Industry Association, IEEE EPS Beijing Chapter and Beijing Faith Information Consultant Ltd. More than 600 delegates from China, the United States, Sweden, Singapore, Japan, Netherlands and many other countries and regions, including experts, scholars and business representatives participated in the event.
The IEEE SA is considering forming a Pre-standards Reusable Electronics Packaging Activity under the IEEE SA Industry Connections Program to explore development of standards and guidelines for reusable electronics packaging. The IEEE SA Industry Connections Program provides a neutral environment where individuals, entities, partners, and competitors can come together and work on shared problems. Pre-standards Activities explore whether sufficient interest and resources exist to develop a standard and if so draft a proposal for an IEEE standards project. The Pre-standards Activity will address the following:
·Potential market acceptance of the standards project, including technical feasibility
·Relationship to related standards, if known, including its distinct identity from other projects
·Viable leadership and participation
·Realistic scope and objectives
If you would like to participate in this project, or want to learn more about it, please contact Joan Woolery at email@example.com
Yasumitsu Orii, High Density Substrates and Boards TC Chair
The High Density Substrates ＆ Boards technical committee (TC-6) of the Electronics Packaging Society EPS is focusing on high-speed and high-density interconnect technologies, based on advanced material-, process-, structure-, and design-technologies. Application areas are ICTs, mobile electronics, automobiles/power electronics, and healthcare. High density substrates and boards are the key components placed in the center of the equipment and always need to be evolved correspondingly to the cutting edge technologies in electrical, optical, and thermal fields.
Patrick McCluskey, EPS Power & Energy Technical Committee Chair
Heterogeneous integration (HI) is not possible without a source of power for the multiple devices and components involved. While it is possible to supply this power externally to one or more devices, it is typically advantageous to integrate the conversion and distribution of this power into the HI system. This makes power delivery one of the most critical elements in an HI system. HI also provides significant advantages for power electronics as it permits wide bandgap power devices, which surpass silicon in power handling capability, efficiency, and operating temperature, to be integrated with silicon control, logic, and memory devices and with lower operating temperature passive devices. Nevertheless, HI of power electronics comes with a raft of challenges for SiP designers, as the power electronics require space, generate heat, and can cause electrical noise in the circuits.